资源列表
[VHDL编程] convolution
说明:Source code for convolution of two complex number is written in Verilog language<bcd> 在 2024-07-06 上传 | 大小:1024 | 下载:0
[VHDL编程] UART_Send_handle
说明:这是一个很好的基于verilog的串口通信422模块,已经经过多次验证,绝对可靠,可直接使用,本人已在工程中多次使用,无误差-This is a good serial communication based on Verilog 422 module, has been repeatedly verified, absolutely reliable, can be used directly, I have repeatedly u<yupeng> 在 2024-07-06 上传 | 大小:1024 | 下载:0
[VHDL编程] alphabeta_transform
说明:alpha beta transformation, for FPGA synthesis and implementation<wahib> 在 2024-07-06 上传 | 大小:1024 | 下载:0
[VHDL编程] Filter_Convolution_Example
说明:Example of a convolution filter implemented in Vivado HLS, the high level synthesis tool Xilinx-Example of a convolution filter implemented in Vivado HLS, the high level synthesis tool Xilinx<rickyalbert> 在 2024-07-06 上传 | 大小:1024 | 下载:0