资源列表
[VHDL编程] alphabeta_transform
说明：alpha beta transformation, for FPGA synthesis and implementation<wahib> 在 2024-12-23 上传 | 大小：1kb | 下载：0
[VHDL编程] Filter_Convolution_Example
说明：Example of a convolution filter implemented in Vivado HLS, the high level synthesis tool Xilinx-Example of a convolution filter implemented in Vivado HLS, the high level synthesis tool Xilinx<rickyalbert> 在 2024-12-23 上传 | 大小：1kb | 下载：0
[VHDL编程] behavioral-hmwk5
说明：Design a synchronous circuit which monitors a 3-bit code as the input. If the code has a constant value in four consecutive clock cycles, a flag is activated.<mafa87> 在 2024-12-23 上传 | 大小：1kb | 下载：0
[VHDL编程] code-hmwk7
说明：Make the required flag signals using the input clock signal (clk) and input flag (TKN). Whenever the TKN signal is activated, a sequence of activation of flag signals should be performed based on the timing diagram<mafa87> 在 2024-12-23 上传 | 大小：1kb | 下载：0
[VHDL编程] hmwk3try.vhd
说明：Design a circuit that take three N-Bit binary numbers as inputs and calculate the average of the largest number and the smallest number as the output. Note that the length of the input numbers should be defined varia<mafa87> 在 2024-12-23 上传 | 大小：1kb | 下载：0
[VHDL编程] CMOS_interface
说明：CMOS Sensor 并行图像接收模块-CMOS Sensor input module<唐> 在 2024-12-23 上传 | 大小：1kb | 下载：0