资源列表
[VHDL编程] UART_Send_handle
说明：这是一个很好的基于verilog的串口通信422模块，已经经过多次验证，绝对可靠，可直接使用，本人已在工程中多次使用，无误差-This is a good serial communication based on Verilog 422 module, has been repeatedly verified, absolutely reliable, can be used directly, I have repeatedly u<yupeng> 在 2025-04-28 上传 | 大小：1kb | 下载：0
[VHDL编程] alphabeta_transform
说明：alpha beta transformation, for FPGA synthesis and implementation<wahib> 在 2025-04-28 上传 | 大小：1kb | 下载：0
[VHDL编程] Filter_Convolution_Example
说明：Example of a convolution filter implemented in Vivado HLS, the high level synthesis tool Xilinx-Example of a convolution filter implemented in Vivado HLS, the high level synthesis tool Xilinx<rickyalbert> 在 2025-04-28 上传 | 大小：1kb | 下载：0
[VHDL编程] behavioral-hmwk5
说明：Design a synchronous circuit which monitors a 3-bit code as the input. If the code has a constant value in four consecutive clock cycles, a flag is activated.<mafa87> 在 2025-04-28 上传 | 大小：1kb | 下载：0
[VHDL编程] code-hmwk7
说明：Make the required flag signals using the input clock signal (clk) and input flag (TKN). Whenever the TKN signal is activated, a sequence of activation of flag signals should be performed based on the timing diagram<mafa87> 在 2025-04-28 上传 | 大小：1kb | 下载：0
[VHDL编程] hmwk3try.vhd
说明：Design a circuit that take three N-Bit binary numbers as inputs and calculate the average of the largest number and the smallest number as the output. Note that the length of the input numbers should be defined varia<mafa87> 在 2025-04-28 上传 | 大小：1kb | 下载：0