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[VHDL编程UART_Send_handle

说明:这是一个很好的基于verilog的串口通信422模块,已经经过多次验证,绝对可靠,可直接使用,本人已在工程中多次使用,无误差-This is a good serial communication based on Verilog 422 module, has been repeatedly verified, absolutely reliable, can be used directly, I have repeatedly u
<yupeng> 在 2025-04-07 上传 | 大小:1kb | 下载:0

[VHDL编程fir25

说明:用VDHL写的25阶对称FIR滤波器,在塞克隆3FPGA下验证没有问题(AD采样时钟50Mhz,这个对硬件设计有点要求),里面调用官方乘法器API,要节省资源可以采用CSD编码转换乘法器,可以减少一半以上的资源-VDHL written by a 25th order symmetric FIR filter in Seke Long 3FPGA under verify that no problem (AD sampling clo
<wangjin> 在 2025-04-07 上传 | 大小:1kb | 下载:0

[VHDL编程SEG_CLOCK

说明:seg clk seg clk seg clk-seg clkseg clkseg clkseg clkseg clk
<yunU> 在 2025-04-07 上传 | 大小:1kb | 下载:0

[VHDL编程alphabeta_transform

说明:alpha beta transformation, for FPGA synthesis and implementation
<wahib> 在 2025-04-07 上传 | 大小:1kb | 下载:0

[VHDL编程myAdc9248

说明:CycloneIV控制采样芯片AD9248-20MHz,VHDL语言-CycloneIV control sampling chip AD9248-20MHz, VHDL language
<wineworm> 在 2025-04-07 上传 | 大小:1kb | 下载:1

[VHDL编程Filter_Convolution_Example

说明:Example of a convolution filter implemented in Vivado HLS, the high level synthesis tool Xilinx-Example of a convolution filter implemented in Vivado HLS, the high level synthesis tool Xilinx
<rickyalbert> 在 2025-04-07 上传 | 大小:1kb | 下载:0

[VHDL编程synd

说明:Syndrome calculator basic unit for reed solomon decoder in verilog language
<humberto> 在 2025-04-07 上传 | 大小:1kb | 下载:0

[VHDL编程behavioral-hmwk5

说明:Design a synchronous circuit which monitors a 3-bit code as the input. If the code has a constant value in four consecutive clock cycles, a flag is activated.
<mafa87> 在 2025-04-07 上传 | 大小:1kb | 下载:0

[VHDL编程code

说明:Design the logic required for a “Dancing Light” system including 5 lights which are turned on repeatedly
<mafa87> 在 2025-04-07 上传 | 大小:1kb | 下载:0

[VHDL编程code-hmwk7

说明:Make the required flag signals using the input clock signal (clk) and input flag (TKN). Whenever the TKN signal is activated, a sequence of activation of flag signals should be performed based on the timing diagram
<mafa87> 在 2025-04-07 上传 | 大小:1kb | 下载:0

[VHDL编程hmwk3try.vhd

说明:Design a circuit that take three N-Bit binary numbers as inputs and calculate the average of the largest number and the smallest number as the output. Note that the length of the input numbers should be defined varia
<mafa87> 在 2025-04-07 上传 | 大小:1kb | 下载:0

[VHDL编程lcdct

说明:at070tn83驱动 驱动 驱动 -driver of the lcd
<sdk> 在 2025-04-07 上传 | 大小:1kb | 下载:0
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