资源列表
[VHDL编程] behavioral-hmwk5
说明：Design a synchronous circuit which monitors a 3-bit code as the input. If the code has a constant value in four consecutive clock cycles, a flag is activated.<mafa87> 在 2024-07-06 上传 | 大小：1024 | 下载：0
[VHDL编程] code-hmwk7
说明：Make the required flag signals using the input clock signal (clk) and input flag (TKN). Whenever the TKN signal is activated, a sequence of activation of flag signals should be performed based on the timing diagram<mafa87> 在 2024-07-06 上传 | 大小：1024 | 下载：0
[VHDL编程] hmwk3try.vhd
说明：Design a circuit that take three N-Bit binary numbers as inputs and calculate the average of the largest number and the smallest number as the output. Note that the length of the input numbers should be defined varia<mafa87> 在 2024-07-06 上传 | 大小：1024 | 下载：0
[VHDL编程] CMOS_interface
说明：CMOS Sensor 并行图像接收模块-CMOS Sensor input module<唐> 在 2024-07-06 上传 | 大小：1024 | 下载：0
[VHDL编程] ADS2807_Ctrl
说明：ADS2807控制,模块功能：取回控制字，控制AD采样速率和AD的地址发生器-ADS2807 control, module function: retrieve control word, control AD sampling rate and AD address<王亚斌> 在 2024-07-06 上传 | 大小：1024 | 下载：0
[VHDL编程] fast_antilog_latest.tar
说明：运行速度不如我的日志代码：166MHz，对于日志的250MHz。 注册输入会带来。 采取与日志相同的资源。-Doesn t run quite as fast as my Log code: 166MHz, vs. 250MHz for the log. Registering the input would bring that up. Takes about the same resources as the log.<asdtgg> 在 2024-07-06 上传 | 大小：1024 | 下载：0
[VHDL编程] pluse_count
说明：以利用FPGA系统时钟分频对定时器进行配置和定时操作。-To take advantage of the FPGA system clock frequency division for timer configuration and operation regularly<KO> 在 2024-07-06 上传 | 大小：1024 | 下载：0
[VHDL编程] Register.vhd
说明：This file is an asynchronous vhdl Register. It registers the input vector into the output vector when the Enable variable is high.<keklaquoi> 在 2024-07-06 上传 | 大小：1024 | 下载：0