资源列表

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[VHDL编程register

说明:用Verilog实现了一个基本寄存器,并且用仿真和led灯来显示了读写数据。-Using Verilog to achieve a basic register, and led lights and simulation to show the read and write data.
<east> 在 2024-12-23 上传 | 大小:1kb | 下载:0

[VHDL编程8a

说明:2 Flip Flops in VHDL
<Thiago Amaral> 在 2024-12-23 上传 | 大小:1kb | 下载:0

[VHDL编程soma_loka

说明:Sum make in vhdl code
<Thiago Amaral> 在 2024-12-23 上传 | 大小:1kb | 下载:0

[VHDL编程rs_232

说明:Comunication rs232 in vhdl
<Thiago Amaral> 在 2024-12-23 上传 | 大小:1kb | 下载:0

[VHDL编程equalizer

说明:This the code for the channel equalizer and the test bench for this in the verilog code.-This is the code for the channel equalizer and the test bench for this in the verilog code.
<rion> 在 2024-12-23 上传 | 大小:1kb | 下载:0

[VHDL编程convolution

说明:This the code for the convolutional and the test bench for this in the verilog code.-This is the code for the convolutional and the test bench for this in the verilog code.
<rion> 在 2024-12-23 上传 | 大小:1kb | 下载:0

[VHDL编程demapperSharp1(16QAM)

说明:This the code for the demapper in the verilog code.-This is the code for the demapper in the verilog code.
<rion> 在 2024-12-23 上传 | 大小:1kb | 下载:0

[VHDL编程mapperSharp1(16QAM)

说明:This the code for the mapper in the verilog code.-This is the code for the mapper in the verilog code.
<rion> 在 2024-12-23 上传 | 大小:1kb | 下载:0

[VHDL编程key_test

说明:采样按键输入,按20ms周期实现按键毛刺消除功能-Sampling key value, to achieve key-glitch elimination function
<钟庆> 在 2024-12-23 上传 | 大小:1kb | 下载:0

[VHDL编程vending-machine

说明:to increase the speed/Performance of the system the UT (Urdhva Triyambhayam) multiplier is used. UT Multiplier [10] is an cient methodology of Indian mathematics as it contains 16 SUTRAS (formulae). A high speed mu
<sid> 在 2024-12-23 上传 | 大小:1kb | 下载:0

[VHDL编程mealy_0011_detector

说明:Key detector a given bit stream-Key detector a given bit stream
<Toi> 在 2024-12-23 上传 | 大小:1kb | 下载:0

[VHDL编程TB_Read_Write_File_vhd

说明:Simplified VHDL testbench: Read/Write from/to Text File.
<AhMahdi> 在 2024-12-23 上传 | 大小:1kb | 下载:0
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