[VHDL编程] COMB

说明：We use port map statement to achieve the structural model (components instantiations). The following example shows how to write the program to incorporate multiple components in the design of a more complex circuit. In o
<sam> 在 2024-11-08 上传 | 大小：1kb | 下载：0

[VHDL编程] CALIBRATION

说明：Calibration is a comparison between measurements – one of known magnitude or correctness made or set with one device and another measurement made in as similar a way as possible with a second device. The device with the
<GOPALAKRISHNAN E> 在 2024-11-08 上传 | 大小：1kb | 下载：0

[VHDL编程] Projects

说明：this is sub and adder in vhdl &writed in ISE
<mohammad> 在 2024-11-08 上传 | 大小：1kb | 下载：0

[VHDL编程] Array-multiplier

说明：Array muiltiplier verilog code.. 4 bit two inputs with 8 bit outputs
<Prashanth R> 在 2024-11-08 上传 | 大小：1kb | 下载：0

[VHDL编程] pid

说明：pid controller design based vhdl code in xilinx code-pid controller design based vhdl code in xilinx code.....................
<GOPALAKRISHNAN E> 在 2024-11-08 上传 | 大小：1kb | 下载：0

[VHDL编程] pwm_auto

说明：PWM for VHDL program
<khefin> 在 2024-11-08 上传 | 大小：1kb | 下载：0

[VHDL编程] verilog_receiver

说明：标准的verilog rs232 接收功能通讯源码，测试可用，已经在实际系统开发中使用。-Standard verilog rs232 reception communications source, testing is available, have been used in the actual system development.
<111111> 在 2024-11-08 上传 | 大小：1kb | 下载：0

[VHDL编程] counter_vhd

说明：An asynchronous (ripple) counter is a single d-type flip-flop, with its J (data) input fed its own inverted output. This circuit can store one bit, and hence can count zero to one before it overflows (starts over 0). Thi
<GOPALAKRISHNAN E> 在 2024-11-08 上传 | 大小：1kb | 下载：0

[VHDL编程] counter_vhd

说明：Counter is used to count the value of the memory register in the digital circuits-Counter is used to count the value of the memory register in the digital circuits....
<GOPALAKRISHNAN E> 在 2024-11-08 上传 | 大小：1kb | 下载：0

[VHDL编程] counter_14uou

说明：Counter wikipediya information will help you to understand about this program-Counter wikipediya information will help you to understand about this program
<GOPALAKRISHNAN E> 在 2024-11-08 上传 | 大小：1kb | 下载：0

[VHDL编程] PWM

说明：此程序利用FPGA芯片的内部时钟，根据输入信号，产生占空比可调的方波信号。-This program uses the FPGA chip s internal clock, according to the input signal to generate variable duty cycle square wave signal.
<lmy> 在 2024-11-08 上传 | 大小：1kb | 下载：0

[VHDL编程] 3Digit_7segment_ind_decoder

说明：3 Digit BCD to 7 segment indicator decoder
<Sergey> 在 2024-11-08 上传 | 大小：1kb | 下载：0