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[VHDL编程rs232-code

说明:RS232 serial convertor to tranfer the serial data
<rahulshandilya1> 在 2024-11-19 上传 | 大小:2kb | 下载:0

[VHDL编程piccolo

说明:piccolo 密码算法的Verilog实现-piccolo algorithm
<朴巍> 在 2024-11-19 上传 | 大小:2kb | 下载:0

[VHDL编程gtx_drp

说明:高速串行设计FPGA-GTX IP设置生成drp模块,可动态配置速率2.4Gbps,1.2Gbps,0.6Gbps,自适应链接-High-speed serial design FPGA-GTX IP setting generation drp module, dynamically configurable rate 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link
<周召涛> 在 2024-11-19 上传 | 大小:2kb | 下载:0

[VHDL编程controller

说明: Simple Microprocessor Design (ESD Book Chapter 3) Copyright 2001 Weijun Zhang Controller (control logic plus state register) VHDL FSM modeling- Simple Microprocessor Design (ESD Book Chapter 3) Copyrig
<mohamed> 在 2024-11-19 上传 | 大小:2kb | 下载:0

[VHDL编程Controller(FSM)

说明: Simple Bridge (ESD book figure 2.14) by Weijun Zhang, 04/2001 RT level design using Controller(FSM) + DataPath- Simple Bridge (ESD book figure 2.14) by Weijun Zhang, 04/2001 RT level design using
<mohamed> 在 2024-11-19 上传 | 大小:2kb | 下载:0

[VHDL编程GCD-CALCULATOR

说明: GCD CALCULATOR (ESD book figure 2.11) Weijun Zhang, 04/2001 we can put all the components in one document(gcd2.vhd) or put them in separate files this is the example of RT level modeling (FSM + DataP
<mohamed> 在 2024-11-19 上传 | 大小:2kb | 下载:0

[VHDL编程scsa

说明:Speculative variable latency adders have attracted strong interest thanks to their capability to reduce average delay compared to traditional architectures. This proposes a novel variable latency speculative adder based
<preethi/charu> 在 2024-11-19 上传 | 大小:2kb | 下载:0

[VHDL编程Segmentation-4G

说明:Segmentation of the 4G standard
<sherif> 在 2024-11-19 上传 | 大小:2kb | 下载:0

[VHDL编程mealy_state_machine_v

说明:mealy状态机示例代码,可以在此代码上学期规范的状态机写法-mealy state machine sample code, this code can be on a state machine specification semester wording
<tiangang> 在 2024-11-19 上传 | 大小:2kb | 下载:0

[VHDL编程moore_state_machine_v

说明:moor状态机的示例代码,再次基础上可以学习标准的状态机写法-moor state machine sample code, we can once again learning standards based on the wording of the state machine
<tiangang> 在 2024-11-19 上传 | 大小:2kb | 下载:0

[VHDL编程FEJQR03IHWIQ3I9

说明:smart fan project for vhdl 5 part(2)
<baris> 在 2024-11-19 上传 | 大小:2kb | 下载:0

[VHDL编程FVLI1QNIHWIQ3GD

说明:smart fan project for vhdl 5 part(xdc)
<baris> 在 2024-11-19 上传 | 大小:2kb | 下载:0
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