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[VHDL编程dffwewe

说明:自己刚编写的vhdl语言来实现的D触发器,自我感觉还可以,也通过了编译,如果有需要就下载去看看吧-just prepared their own language to achieve vhdl D flip-flop, but also a sense of self, but also through a compiler, If there is a need to look at the downloaded Look here
<wenjun> 在 2024-10-07 上传 | 大小:1024 | 下载:0

[VHDL编程beipin_4

说明:自己编写的vhdl语言来实现的四倍频电路,自我感觉还可以,也通过了编译,如果有需要就下载去看看吧-prepared vhdl own language to achieve the four frequency circuit, a sense of self, can also, through a compiler, If there is a need to look at the downloaded Look here
<wenjun> 在 2024-10-07 上传 | 大小:2048 | 下载:0

[VHDL编程lpm_inv0

说明:自己编写的vhdl语言来实现的lpm_inv0电路,自我感觉还可以,也通过了编译,如果有需要就下载去看看吧-prepared vhdl own language to achieve the lpm_inv0 circuit, but also a sense of self, also passed the compiler, if there is a need to look at the downloaded Look here
<wenjun> 在 2024-10-07 上传 | 大小:1024 | 下载:0

[VHDL编程74138_0

说明:这是老师给的3—8译码器的源程序,自己刚才调试过了,真的成功了,哈哈……,有需要就看看吧-This the teacher for the 3-8 decoder source, have their own testing before, and really successful, ha ha ... there is a need to watch it!
<wenjun> 在 2024-10-07 上传 | 大小:1024 | 下载:0

[VHDL编程4_10_vhdl

说明:这是老师给但计数器程序,经过自己刚才调试过了,真的成功了,哈哈……,有需要就看看吧-This the teacher but to counter procedures, testing himself just over a really successful, ha ha ... there is a need to watch it!
<wenjun> 在 2024-10-07 上传 | 大小:1024 | 下载:0

[VHDL编程VerilogHDLjihe

说明:王金明的Verilog HDL程序集合,包含各个常用的程序-guo Verilog HDL procedures set includes all commonly used procedures
<weishenghe> 在 2024-10-07 上传 | 大小:113664 | 下载:0

[VHDL编程I2C_loader

说明:用FPGA做主控制器,对IIC从设备配置参数的源程序。Xilinx提供-FPGA master controller, right from the IIC equipment configuration parameters of the source. Xilinx offer
<cloud> 在 2024-10-07 上传 | 大小:93184 | 下载:0

[VHDL编程422_to_444

说明:YUV422转YUV444的FPGA插植算法,由Xilinx提供-YUV422 to YUV444 FPGA implantation algorithm provided by Xilinx
<cloud> 在 2024-10-07 上传 | 大小:70656 | 下载:0

[VHDL编程KPCSMII

说明:Xillinx 的8位MCU软核的源代码,可在VertexII上运行,对CPU设计人员有很*意义-Xillinx the eight MCU soft-core source code can be run in VertexII. CPU designers to have great reference value
<cloud> 在 2024-10-07 上传 | 大小:343040 | 下载:0

[VHDL编程lf_decode

说明:检测BT.656视频格式中内含的同步信号,可分离出行场同步信号。-detection R BT.656 video format containing the synchronization signal separable travel market synchronous signal.
<cloud> 在 2024-10-07 上传 | 大小:87040 | 下载:0

[VHDL编程ycrcb_rgb

说明:YUV转RGB的源程序,使用到了硬件加速器,可利用FGPA的乘法器加速处理速度。-YUV to RGB source, the use of a hardware accelerator, FGPA can be used to speed up the processing speed multiplier.
<cloud> 在 2024-10-07 上传 | 大小:107520 | 下载:0

[VHDL编程deinterlace

说明:Xilinx提供的一种利用线缓存进行插值的隔行变逐行程序,比普通算法效果有很大改进。-Xilinx to provide a linear interpolation for the cache interlaced progressive change procedures, than ordinary algorithm results are greatly improved.
<cloud> 在 2024-10-07 上传 | 大小:99328 | 下载:0
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