资源列表
[VHDL编程] qiangdaqilunwen
说明:verilog hdl实现的三路抢答器,一个复位键,八个数码管,五个LED灯,晶振为12 MHz 采用CPLD 器件为ALTERA 的EPM7064SL-44芯片 -verilog hdl implementation of three-way Responder, a reset button, eight digital control, five LED lights, crystal is 12 MHz ALT<李瑞芳> 在 2025-03-06 上传 | 大小:91kb | 下载:0
[VHDL编程] HDB3
说明:基于FPGA的HDB3码的译码器代码,主要用于译码器-HDB3 yards on FPGA decoder code, mainly for the decoder<cenmingcan> 在 2025-03-06 上传 | 大小:1kb | 下载:0
[VHDL编程] i2c_master_slave_core_latest.tar
说明:This design is Wishbone compatible I2C core. This core can work as I2C master as well as slave. VMM Test-bench is also available.<Andrey> 在 2025-03-06 上传 | 大小:4.35mb | 下载:0
[VHDL编程] tiny64_latest.tar
说明:Descr iption Tiny64 A 64-Bit RISC CPU with minial resource usage. Every opcode is executed in 2 clock cycles. The word size is configurable via XLEN from 32 up to the FPGA limit. The assembler supports also diff<Andrey> 在 2025-03-06 上传 | 大小:22kb | 下载:0
[VHDL编程] can_latest.tar
说明:Controller Area Network or CAN is a control network protocol from Bosch that has found wide use in Industrial Automation and the Automotive Industry. Most of the patents of CAN are owned by Bosch and although th<Andrey> 在 2025-03-06 上传 | 大小:1.12mb | 下载:0
[VHDL编程] a_vhd_16550_uart_latest.tar
说明:A UART that is compatible with the industry standard 16550D Includes wrappers for the Wishbone and AMBA APB busses<Andrey> 在 2025-03-06 上传 | 大小:117kb | 下载:0