资源列表
[VHDL编程] mux
说明:verilog code it is about multiplexer<myank jaiswal> 在 2024-10-15 上传 | 大小:104448 | 下载:0
[VHDL编程] VD_212_correction
说明:对田耘等所著《无线通信FPGA设计》中第324页代码错误进行了更正,并对代码进行了注释。同时给出了测试激励文件。-Tian Yun and other book Wireless Communications FPGA design on page 324 of the code error has been corrected, and the code of the comments.At the same time gives<LIU-Jianlinag> 在 2024-10-15 上传 | 大小:244736 | 下载:0
[VHDL编程] master_bla
说明:master bla altera quartus II version 15<wira> 在 2024-10-15 上传 | 大小:2048 | 下载:0
[VHDL编程] altdq_dqs2
说明:altera ip a ltera ip-altera ip altera ip altera ip<wira> 在 2024-10-15 上传 | 大小:2255872 | 下载:0
[VHDL编程] descore_latest.tar
说明:VHDL implementation of the classic DES block cipher (interactive architecture)<hj> 在 2024-10-15 上传 | 大小:6144 | 下载:0
[VHDL编程] pwm_latest.tar
说明:pulse width modulator, work as one PWM or one timer. 16 bit main counter<hj> 在 2024-10-15 上传 | 大小:128000 | 下载:0
[VHDL编程] scalable_arbiter_latest.tar
说明:a scalable synchronous round-robin arbiter. The arbiter is designed to run at reasonable clock speed with up to hundreds of request lines, and it grants in just a few clock cycles.<hj> 在 2024-10-15 上传 | 大小:53248 | 下载:0
[VHDL编程] statled_latest.tar
说明:a simple module to get the most of your on board heartbeat LED change or add more sequences easily in parameters file<hj> 在 2024-10-15 上传 | 大小:2048 | 下载:0