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[VHDL编程counter-achieved-by-verilog

说明:该代码用Verilog语言实现了计数功能,主要实现29为计数,已通过仿真验证。-The code in Verilog realize the counting function, the main achievement of 29 counts, has been verified by simulation.
<daruili> 在 2024-11-15 上传 | 大小:2kb | 下载:0

[VHDL编程divider-achieved-by-verilog

说明:该代码用Verilog语言实现了分频功能,主要实现对输入时钟的54分频,已通过仿真验证。-The code in Verilog realize the crossover functions, the main achievement of the input clock frequency of 54 minutes, has been verified by simulation.
<daruili> 在 2024-11-15 上传 | 大小:2kb | 下载:0

[VHDL编程shfiting-output-achieved-by-verilog

说明:该代码用Verilog语言实现了移位输出功能,主要实现对输入信号进行移位输出,已通过仿真验证。-The code in Verilog realize the shift output function, the main achievement of the input signal shift output has been verified by simulation.
<daruili> 在 2024-11-15 上传 | 大小:3kb | 下载:0

[VHDL编程weimafashengqi-achieved-by-verilog

说明:该代码用Verilog语言实现了M序列的伪码产生,伪码特征方程为X13 +X7+X5+1,已通过仿真验证。-The code in Verilog realize the M-sequence pseudo-code generation, pseudo-code characteristic equation for the X13+ X7+ X5+ 1, it has been verified by simulation.
<daruili> 在 2024-11-15 上传 | 大小:3kb | 下载:0

[VHDL编程UART_send

说明:串口单字节发送数据。已测试通过。编程预言是Verilog。-Single-byte serial transmit data. It has been tested. Programming language is Verilog.
<毛毛> 在 2024-11-15 上传 | 大小:1kb | 下载:0

[VHDL编程UART_rec

说明:用Verilog语言写的串口接收程序。通过串口助手发送数据,在数据输出端可以看到发送的数据。(需要自己分配FPGA引脚)-Verilog language used to write the serial receiver. Send data through the serial port assistant. It can be seen at the data output terminal of the data transmi
<毛毛> 在 2024-11-15 上传 | 大小:1kb | 下载:0

[VHDL编程my_cpu

说明:计算机组成原理实验代码:单周期Cpu设计,附上检测指令, 在ISE 14.4通过检测-Computer Composition Theory Experiment Code: Cpu single-cycle design, attach detection command, by detecting the ISE 14.4
<李旭东> 在 2024-11-15 上传 | 大小:2.22mb | 下载:0

[VHDL编程AlertLogPkg

说明:osvvm alert packages that is helpful for vhdl verification
<anupam maurya> 在 2024-11-15 上传 | 大小:13kb | 下载:0

[VHDL编程CoveragePkg

说明:osvvm coverage packages that is helpful for vhdl verification
<anupam maurya> 在 2024-11-15 上传 | 大小:21kb | 下载:0

[VHDL编程frequency-generation

说明:基于VHDL语言的分频器,输入四位比特控制产生相应的输出频率。-Frequency divider based on VHDL language, input control four bits to produce the corresponding output frequency.
<jianyong> 在 2024-11-15 上传 | 大小:3.2mb | 下载:0

[VHDL编程traffic

说明:用quartusII编写,实现双向交通灯运行,仿真ok,可以直接下板子-Quartus II with a written two-way traffic lights running simulation ok, directly under the board
<Wane> 在 2024-11-15 上传 | 大小:1.36mb | 下载:0

[VHDL编程example19-LCD1602

说明:基于verilog HDL的LCD1602显示程序,调试通过,可直接调用。-Based verilog HDL of LCD1602 display program, debugging through, can be called directly.
<lwb> 在 2024-11-15 上传 | 大小:962kb | 下载:0
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