文件名称:uart16550
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uart16550 ＩＰ核
ＨＤＬ源代码，对设计自己uart的人员和学习串口通讯有一定的参考价值！其中，附有详细的所明文档！-uart16550 IP HDL source code, uart to design their own study of serial communication and has some reference value. Which, with detailed documentation as prescribed!
ＨＤＬ源代码，对设计自己uart的人员和学习串口通讯有一定的参考价值！其中，附有详细的所明文档！-uart16550 IP HDL source code, uart to design their own study of serial communication and has some reference value. Which, with detailed documentation as prescribed!
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压缩包 : 71477187uart16550.rar 列表 uart16550\CVS\Root uart16550\CVS\Repository uart16550\CVS\Entries uart16550\CVS uart16550\Doc\CVS\Root uart16550\Doc\CVS\Repository uart16550\Doc\CVS\Entries uart16550\Doc\CVS uart16550\Doc\CHANGES.txt uart16550\Doc\UART_spec.pdf uart16550\Doc\src\CVS\Root uart16550\Doc\src\CVS\Repository uart16550\Doc\src\CVS\Entries uart16550\Doc\src\CVS uart16550\Doc\src\UART_spec.doc uart16550\Doc\src uart16550\Doc uart16550\bench\CVS\Root uart16550\bench\CVS\Repository uart16550\bench\CVS\Entries uart16550\bench\CVS uart16550\bench\verilog\CVS\Root uart16550\bench\verilog\CVS\Repository uart16550\bench\verilog\CVS\Entries uart16550\bench\verilog\CVS uart16550\bench\verilog\readme.txt uart16550\bench\verilog\uart_device.v uart16550\bench\verilog\uart_device_utilities.v uart16550\bench\verilog\uart_log.v uart16550\bench\verilog\uart_test.v uart16550\bench\verilog\uart_testbench.v uart16550\bench\verilog\uart_testbench_defines.v uart16550\bench\verilog\uart_testbench_utilities.v uart16550\bench\verilog\uart_wb_utilities.v uart16550\bench\verilog\vapi.log uart16550\bench\verilog\wb_mast.v uart16550\bench\verilog\wb_master_model.v uart16550\bench\verilog\wb_model_defines.v uart16550\bench\verilog\test_cases\CVS\Root uart16550\bench\verilog\test_cases\CVS\Repository uart16550\bench\verilog\test_cases\CVS\Entries uart16550\bench\verilog\test_cases\CVS uart16550\bench\verilog\test_cases\uart_int.v uart16550\bench\verilog\test_cases uart16550\bench\verilog uart16550\bench\vhdl\CVS\Root uart16550\bench\vhdl\CVS\Repository uart16550\bench\vhdl\CVS\Entries uart16550\bench\vhdl\CVS uart16550\bench\vhdl\.keepme uart16550\bench\vhdl uart16550\bench uart16550\fv\CVS\Root uart16550\fv\CVS\Repository uart16550\fv\CVS\Entries uart16550\fv\CVS uart16550\fv\.keepme uart16550\fv uart16550\lint\CVS\Root uart16550\lint\CVS\Repository uart16550\lint\CVS\Entries uart16550\lint\CVS uart16550\lint\bin\CVS\Root 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