文件名称:uart16550
介绍说明－－下载内容均来自于网络，请自行研究使用
uart source code from opencore
(系统自动生成,下载前可以参看下载内容)
下载文件列表
uart16550
.........\bench
.........\.....\CVS
.........\.....\...\Entries
.........\.....\...\Repository
.........\.....\...\Root
.........\.....\verilog
.........\.....\.......\CVS
.........\.....\.......\...\Entries
.........\.....\.......\...\Repository
.........\.....\.......\...\Root
.........\.....\.......\uart_test.v
.........\.....\vhdl
.........\.....\....\.keepme
.........\.....\....\CVS
.........\.....\....\...\Entries
.........\.....\....\...\Repository
.........\.....\....\...\Root
.........\Doc
.........\...\CHANGES.txt
.........\...\CVS
.........\...\...\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\src
.........\...\...\CVS
.........\...\...\...\Entries
.........\...\...\...\Repository
.........\...\...\...\Root
.........\...\...\UART_spec.doc
.........\...\UART_spec.pdf
.........\fv
.........\..\.keepme
.........\..\CVS
.........\..\...\Entries
.........\..\...\Repository
.........\..\...\Root
.........\lint
.........\....\bin
.........\....\...\.keepme
.........\....\...\CVS
.........\....\...\...\Entries
.........\....\...\...\Repository
.........\....\...\...\Root
.........\....\CVS
.........\....\...\Entries
.........\....\...\Repository
.........\....\...\Root
.........\....\log
.........\....\...\.keepme
.........\....\...\CVS
.........\....\...\...\Entries
.........\....\...\...\Repository
.........\....\...\...\Root
.........\....\out
.........\....\...\.keepme
.........\....\...\CVS
.........\....\...\...\Entries
.........\....\...\...\Repository
.........\....\...\...\Root
.........\....\run
.........\....\...\.keepme
.........\....\...\CVS
.........\....\...\...\Entries
.........\....\...\...\Repository
.........\....\...\...\Root
.........\rtl
.........\...\CVS
.........\...\...\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\verilog
.........\...\.......\CVS
.........\...\.......\...\Entries
.........\...\.......\...\Repository
.........\...\.......\...\Root
.........\...\.......\timescale.v
.........\...\.......\uart_defines.v
.........\...\.......\uart_fifo.v
.........\...\.......\uart_receiver.v
.........\...\.......\uart_regs.v
.........\...\.......\uart_top.v
.........\...\.......\uart_transmitter.v
.........\...\.......\uart_wb.v
.........\...\vhdl
.........\...\....\.keepme
.........\...\....\CVS
.........\...\....\...\Entries
.........\...\....\...\Repository
.........\...\....\...\Root
.........\sim
.........\...\CVS
.........\...\...\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\gate_sim
.........\...\........\bin
.........\...\........\...\.keepme
.........\...\........\...\CVS
.........\...\........\...\...\Entries
.........\bench
.........\.....\CVS
.........\.....\...\Entries
.........\.....\...\Repository
.........\.....\...\Root
.........\.....\verilog
.........\.....\.......\CVS
.........\.....\.......\...\Entries
.........\.....\.......\...\Repository
.........\.....\.......\...\Root
.........\.....\.......\uart_test.v
.........\.....\vhdl
.........\.....\....\.keepme
.........\.....\....\CVS
.........\.....\....\...\Entries
.........\.....\....\...\Repository
.........\.....\....\...\Root
.........\Doc
.........\...\CHANGES.txt
.........\...\CVS
.........\...\...\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\src
.........\...\...\CVS
.........\...\...\...\Entries
.........\...\...\...\Repository
.........\...\...\...\Root
.........\...\...\UART_spec.doc
.........\...\UART_spec.pdf
.........\fv
.........\..\.keepme
.........\..\CVS
.........\..\...\Entries
.........\..\...\Repository
.........\..\...\Root
.........\lint
.........\....\bin
.........\....\...\.keepme
.........\....\...\CVS
.........\....\...\...\Entries
.........\....\...\...\Repository
.........\....\...\...\Root
.........\....\CVS
.........\....\...\Entries
.........\....\...\Repository
.........\....\...\Root
.........\....\log
.........\....\...\.keepme
.........\....\...\CVS
.........\....\...\...\Entries
.........\....\...\...\Repository
.........\....\...\...\Root
.........\....\out
.........\....\...\.keepme
.........\....\...\CVS
.........\....\...\...\Entries
.........\....\...\...\Repository
.........\....\...\...\Root
.........\....\run
.........\....\...\.keepme
.........\....\...\CVS
.........\....\...\...\Entries
.........\....\...\...\Repository
.........\....\...\...\Root
.........\rtl
.........\...\CVS
.........\...\...\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\verilog
.........\...\.......\CVS
.........\...\.......\...\Entries
.........\...\.......\...\Repository
.........\...\.......\...\Root
.........\...\.......\timescale.v
.........\...\.......\uart_defines.v
.........\...\.......\uart_fifo.v
.........\...\.......\uart_receiver.v
.........\...\.......\uart_regs.v
.........\...\.......\uart_top.v
.........\...\.......\uart_transmitter.v
.........\...\.......\uart_wb.v
.........\...\vhdl
.........\...\....\.keepme
.........\...\....\CVS
.........\...\....\...\Entries
.........\...\....\...\Repository
.........\...\....\...\Root
.........\sim
.........\...\CVS
.........\...\...\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\gate_sim
.........\...\........\bin
.........\...\........\...\.keepme
.........\...\........\...\CVS
.........\...\........\...\...\Entries