文件名称:uart16550
- 所属分类：
- 串口编程
- 资源属性：
- [PDF]
- 上传时间：
- 2012-11-26
- 文件大小：
- 1.68mb
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- 0次
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- Cloud*****
- 相关连接：
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- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
uart16550 is a 16550 compatible (mostly) UART core.
The bus interface is WISHBONE SoC bus Rev. B.
Features all the standard options of the 16550 UART:
FIFO based operation, interrupt requests and other.
The datasheet can be downloaded from the CVS tree along with the source code. -uart16550 is a 16550 compatible (mostly) UART core.
The bus interface is WISHBONE SoC bus Rev. B.
Features all the standard options of the 16550 UART:
FIFO based operation, interrupt requests and other.
The datasheet can be downloaded from the CVS tree along with the source code.
The bus interface is WISHBONE SoC bus Rev. B.
Features all the standard options of the 16550 UART:
FIFO based operation, interrupt requests and other.
The datasheet can be downloaded from the CVS tree along with the source code. -uart16550 is a 16550 compatible (mostly) UART core.
The bus interface is WISHBONE SoC bus Rev. B.
Features all the standard options of the 16550 UART:
FIFO based operation, interrupt requests and other.
The datasheet can be downloaded from the CVS tree along with the source code.
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(系统自动生成,下载前可以参看下载内容)
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uart16550
.........\branches
.........\tags
.........\....\asyst_2
.........\....\.......\rtl
.........\....\.......\...\verilog
.........\....\.......\...\.......\timescale.v
.........\....\.......\...\.......\uart_debug_if.v
.........\....\.......\...\.......\uart_defines.v
.........\....\.......\...\.......\uart_fifo.v
.........\....\.......\...\.......\uart_receiver.v
.........\....\.......\...\.......\uart_regs.v
.........\....\.......\...\.......\uart_top.v
.........\....\.......\...\.......\uart_transmitter.v
.........\....\.......\...\.......\uart_wb.v
.........\....\.......\...\vhdl
.........\....\.......\...\....\.keepme
.........\....\asyst_3
.........\....\.......\rtl
.........\....\.......\...\verilog
.........\....\.......\...\.......\timescale.v
.........\....\.......\...\.......\uart_debug_if.v
.........\....\.......\...\.......\uart_defines.v
.........\....\.......\...\.......\uart_fifo.v
.........\....\.......\...\.......\uart_receiver.v
.........\....\.......\...\.......\uart_regs.v
.........\....\.......\...\.......\uart_top.v
.........\....\.......\...\.......\uart_transmitter.v
.........\....\.......\...\.......\uart_wb.v
.........\....\.......\...\vhdl
.........\....\.......\...\....\.keepme
.........\....\initial
.........\....\.......\Doc
.........\....\.......\...\UART_spec.pdf
.........\....\.......\verilog
.........\....\.......\.......\FIFO_inc.v
.........\....\.......\.......\timescale.v
.........\....\.......\.......\ToDo.txt
.........\....\.......\.......\UART_defines.v
.........\....\.......\.......\UART_FIFO.v
.........\....\.......\.......\UART_FIFO_t.v
.........\....\.......\.......\UART_regs.v
.........\....\.......\.......\UART_RX_FIFO.v
.........\....\.......\.......\UART_test.v
.........\....\.......\.......\UART_top.v
.........\....\.......\.......\UART_TX_FIFO.v
.........\....\.......\.......\UART_wb.v
.........\....\NewFormat
.........\....\.........\bench
.........\....\.........\.....\verilog
.........\....\.........\.....\.......\uart_test.v
.........\....\.........\doc
.........\....\.........\...\CHANGES.txt
.........\....\.........\...\src
.........\....\.........\...\...\UART_spec.doc
.........\....\.........\...\UART_spec.pdf
.........\....\.........\rtl
.........\....\.........\...\verilog
.........\....\.........\...\.......\timescale.v
.........\....\.........\...\.......\uart_defines.v
.........\....\.........\...\.......\uart_fifo.v
.........\....\.........\...\.......\uart_receiver.v
.........\....\.........\...\.......\uart_regs.v
.........\....\.........\...\.......\uart_top.v
.........\....\.........\...\.......\uart_transmitter.v
.........\....\.........\...\.......\uart_wb.v
.........\....\.........\...\verilog-backup
.........\....\.........\...\..............\timescale.v
.........\....\.........\...\..............\uart_defines.v
.........\....\.........\...\..............\uart_fifo.v
.........\....\.........\...\..............\uart_receiver.v
.........\....\.........\...\..............\uart_regs.v
.........\....\.........\...\..............\uart_top.v
.........\....\.........\...\..............\uart_transmitter.v
.........\....\.........\...\..............\uart_wb.v
.........\....\.........\sim
.........\....\.........\...\rtl_sim
.........\....\.........\...\.......\bin
.........\....\.........\...\.......\...\nc.scr
.........\....\.........\...\.......\...\sim.tcl
.........\....\.........\...\.......\run
.........\....\.........\...\.......\...\run_signalscan
.........\....\.........\...\.......\...\run_sim
.........\....\rel_1
.........\....\.....\bench
.........\....\.....\.....\verilog
.........\....\.....\.....\.......\readme.txt
.........\....\.....\.....\.......\uart_device_if.v
.........\....\.....\.....\.......\uart_device_if_defines.v
.........\....\.....\.....\.......\uart_device_if_memory.v
.........\....\.....\.....\.......\uart_test.v
.........\....\.....\.....\.......\vapi.log
.........\....\.....\.....\.......\wb_mast.v
.........\....\.....\.....\vhdl
.........\....\.....\.....\....\.keepme
.........\....\.....\doc
.........\....\.....\...\C
.........\branches
.........\tags
.........\....\asyst_2
.........\....\.......\rtl
.........\....\.......\...\verilog
.........\....\.......\...\.......\timescale.v
.........\....\.......\...\.......\uart_debug_if.v
.........\....\.......\...\.......\uart_defines.v
.........\....\.......\...\.......\uart_fifo.v
.........\....\.......\...\.......\uart_receiver.v
.........\....\.......\...\.......\uart_regs.v
.........\....\.......\...\.......\uart_top.v
.........\....\.......\...\.......\uart_transmitter.v
.........\....\.......\...\.......\uart_wb.v
.........\....\.......\...\vhdl
.........\....\.......\...\....\.keepme
.........\....\asyst_3
.........\....\.......\rtl
.........\....\.......\...\verilog
.........\....\.......\...\.......\timescale.v
.........\....\.......\...\.......\uart_debug_if.v
.........\....\.......\...\.......\uart_defines.v
.........\....\.......\...\.......\uart_fifo.v
.........\....\.......\...\.......\uart_receiver.v
.........\....\.......\...\.......\uart_regs.v
.........\....\.......\...\.......\uart_top.v
.........\....\.......\...\.......\uart_transmitter.v
.........\....\.......\...\.......\uart_wb.v
.........\....\.......\...\vhdl
.........\....\.......\...\....\.keepme
.........\....\initial
.........\....\.......\Doc
.........\....\.......\...\UART_spec.pdf
.........\....\.......\verilog
.........\....\.......\.......\FIFO_inc.v
.........\....\.......\.......\timescale.v
.........\....\.......\.......\ToDo.txt
.........\....\.......\.......\UART_defines.v
.........\....\.......\.......\UART_FIFO.v
.........\....\.......\.......\UART_FIFO_t.v
.........\....\.......\.......\UART_regs.v
.........\....\.......\.......\UART_RX_FIFO.v
.........\....\.......\.......\UART_test.v
.........\....\.......\.......\UART_top.v
.........\....\.......\.......\UART_TX_FIFO.v
.........\....\.......\.......\UART_wb.v
.........\....\NewFormat
.........\....\.........\bench
.........\....\.........\.....\verilog
.........\....\.........\.....\.......\uart_test.v
.........\....\.........\doc
.........\....\.........\...\CHANGES.txt
.........\....\.........\...\src
.........\....\.........\...\...\UART_spec.doc
.........\....\.........\...\UART_spec.pdf
.........\....\.........\rtl
.........\....\.........\...\verilog
.........\....\.........\...\.......\timescale.v
.........\....\.........\...\.......\uart_defines.v
.........\....\.........\...\.......\uart_fifo.v
.........\....\.........\...\.......\uart_receiver.v
.........\....\.........\...\.......\uart_regs.v
.........\....\.........\...\.......\uart_top.v
.........\....\.........\...\.......\uart_transmitter.v
.........\....\.........\...\.......\uart_wb.v
.........\....\.........\...\verilog-backup
.........\....\.........\...\..............\timescale.v
.........\....\.........\...\..............\uart_defines.v
.........\....\.........\...\..............\uart_fifo.v
.........\....\.........\...\..............\uart_receiver.v
.........\....\.........\...\..............\uart_regs.v
.........\....\.........\...\..............\uart_top.v
.........\....\.........\...\..............\uart_transmitter.v
.........\....\.........\...\..............\uart_wb.v
.........\....\.........\sim
.........\....\.........\...\rtl_sim
.........\....\.........\...\.......\bin
.........\....\.........\...\.......\...\nc.scr
.........\....\.........\...\.......\...\sim.tcl
.........\....\.........\...\.......\run
.........\....\.........\...\.......\...\run_signalscan
.........\....\.........\...\.......\...\run_sim
.........\....\rel_1
.........\....\.....\bench
.........\....\.....\.....\verilog
.........\....\.....\.....\.......\readme.txt
.........\....\.....\.....\.......\uart_device_if.v
.........\....\.....\.....\.......\uart_device_if_defines.v
.........\....\.....\.....\.......\uart_device_if_memory.v
.........\....\.....\.....\.......\uart_test.v
.........\....\.....\.....\.......\vapi.log
.........\....\.....\.....\.......\wb_mast.v
.........\....\.....\.....\vhdl
.........\....\.....\.....\....\.keepme
.........\....\.....\doc
.........\....\.....\...\C