文件名称:uart16550
介绍说明－－下载内容均来自于网络，请自行研究使用
uart16550 ＩＰ核
ＨＤＬ源代码，对设计自己uart的人员和学习串口通讯有一定的参考价值！其中，附有详细的所明文档！-uart16550 IP HDL source code, uart to design their own study of serial communication and has some reference value. Which, with detailed documentation as prescribed!
ＨＤＬ源代码，对设计自己uart的人员和学习串口通讯有一定的参考价值！其中，附有详细的所明文档！-uart16550 IP HDL source code, uart to design their own study of serial communication and has some reference value. Which, with detailed documentation as prescribed!
(系统自动生成,下载前可以参看下载内容)
下载文件列表
uart16550
.........\bench
.........\.....\CVS
.........\.....\...\Entries
.........\.....\...\Repository
.........\.....\...\Root
.........\.....\verilog
.........\.....\.......\CVS
.........\.....\.......\...\Entries
.........\.....\.......\...\Repository
.........\.....\.......\...\Root
.........\.....\.......\readme.txt
.........\.....\.......\test_cases
.........\.....\.......\..........\CVS
.........\.....\.......\..........\...\Entries
.........\.....\.......\..........\...\Repository
.........\.....\.......\..........\...\Root
.........\.....\.......\..........\uart_int.v
.........\.....\.......\uart_device.v
.........\.....\.......\uart_device_utilities.v
.........\.....\.......\uart_log.v
.........\.....\.......\uart_test.v
.........\.....\.......\uart_testbench.v
.........\.....\.......\uart_testbench_defines.v
.........\.....\.......\uart_testbench_utilities.v
.........\.....\.......\uart_wb_utilities.v
.........\.....\.......\vapi.log
.........\.....\.......\wb_mast.v
.........\.....\.......\wb_master_model.v
.........\.....\.......\wb_model_defines.v
.........\.....\vhdl
.........\.....\....\.keepme
.........\.....\....\CVS
.........\.....\....\...\Entries
.........\.....\....\...\Repository
.........\.....\....\...\Root
.........\CVS
.........\...\Entries
.........\...\Repository
.........\...\Root
.........\Doc
.........\...\CHANGES.txt
.........\...\CVS
.........\...\...\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\src
.........\...\...\CVS
.........\...\...\...\Entries
.........\...\...\...\Repository
.........\...\...\...\Root
.........\...\...\UART_spec.doc
.........\...\UART_spec.pdf
.........\fv
.........\..\.keepme
.........\..\CVS
.........\..\...\Entries
.........\..\...\Repository
.........\..\...\Root
.........\lint
.........\....\bin
.........\....\...\.keepme
.........\....\...\CVS
.........\....\...\...\Entries
.........\....\...\...\Repository
.........\....\...\...\Root
.........\....\CVS
.........\....\...\Entries
.........\....\...\Repository
.........\....\...\Root
.........\....\log
.........\....\...\.keepme
.........\....\...\CVS
.........\....\...\...\Entries
.........\....\...\...\Repository
.........\....\...\...\Root
.........\....\out
.........\....\...\.keepme
.........\....\...\CVS
.........\....\...\...\Entries
.........\....\...\...\Repository
.........\....\...\...\Root
.........\....\run
.........\....\...\.keepme
.........\....\...\CVS
.........\....\...\...\Entries
.........\....\...\...\Repository
.........\....\...\...\Root
.........\rtl
.........\...\CVS
.........\...\...\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\verilog
.........\...\.......\CVS
.........\...\.......\...\Entries
.........\...\.......\...\Repository
.........\...\.......\...\Root
.........\...\.......\raminfr.v
.........\...\.......\timescale.v
.........\bench
.........\.....\CVS
.........\.....\...\Entries
.........\.....\...\Repository
.........\.....\...\Root
.........\.....\verilog
.........\.....\.......\CVS
.........\.....\.......\...\Entries
.........\.....\.......\...\Repository
.........\.....\.......\...\Root
.........\.....\.......\readme.txt
.........\.....\.......\test_cases
.........\.....\.......\..........\CVS
.........\.....\.......\..........\...\Entries
.........\.....\.......\..........\...\Repository
.........\.....\.......\..........\...\Root
.........\.....\.......\..........\uart_int.v
.........\.....\.......\uart_device.v
.........\.....\.......\uart_device_utilities.v
.........\.....\.......\uart_log.v
.........\.....\.......\uart_test.v
.........\.....\.......\uart_testbench.v
.........\.....\.......\uart_testbench_defines.v
.........\.....\.......\uart_testbench_utilities.v
.........\.....\.......\uart_wb_utilities.v
.........\.....\.......\vapi.log
.........\.....\.......\wb_mast.v
.........\.....\.......\wb_master_model.v
.........\.....\.......\wb_model_defines.v
.........\.....\vhdl
.........\.....\....\.keepme
.........\.....\....\CVS
.........\.....\....\...\Entries
.........\.....\....\...\Repository
.........\.....\....\...\Root
.........\CVS
.........\...\Entries
.........\...\Repository
.........\...\Root
.........\Doc
.........\...\CHANGES.txt
.........\...\CVS
.........\...\...\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\src
.........\...\...\CVS
.........\...\...\...\Entries
.........\...\...\...\Repository
.........\...\...\...\Root
.........\...\...\UART_spec.doc
.........\...\UART_spec.pdf
.........\fv
.........\..\.keepme
.........\..\CVS
.........\..\...\Entries
.........\..\...\Repository
.........\..\...\Root
.........\lint
.........\....\bin
.........\....\...\.keepme
.........\....\...\CVS
.........\....\...\...\Entries
.........\....\...\...\Repository
.........\....\...\...\Root
.........\....\CVS
.........\....\...\Entries
.........\....\...\Repository
.........\....\...\Root
.........\....\log
.........\....\...\.keepme
.........\....\...\CVS
.........\....\...\...\Entries
.........\....\...\...\Repository
.........\....\...\...\Root
.........\....\out
.........\....\...\.keepme
.........\....\...\CVS
.........\....\...\...\Entries
.........\....\...\...\Repository
.........\....\...\...\Root
.........\....\run
.........\....\...\.keepme
.........\....\...\CVS
.........\....\...\...\Entries
.........\....\...\...\Repository
.........\....\...\...\Root
.........\rtl
.........\...\CVS
.........\...\...\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\verilog
.........\...\.......\CVS
.........\...\.......\...\Entries
.........\...\.......\...\Repository
.........\...\.......\...\Root
.........\...\.......\raminfr.v
.........\...\.......\timescale.v