文件名称:ref-sdr-sdram-verilog
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ref-sdr-sdram-verilog\doc\sdram原理.doc
.....................\readme_sdr_sdram.txt
.....................\sdr_sdram.pdf
.....................\.imulation\sdr_sdram_tb.v
.....................\.ource\altclklock.v
.....................\......\Command.v
.....................\......\compile_all.v
.....................\......\control_interface.v
.....................\......\Params.v
.....................\......\PLL1.v
.....................\......\sdr_data_path.v
.....................\......\sdr_sdram.v
.....................\本参考设计学习总结.doc
.....................\doc
.....................\simulation
.....................\source
ref-sdr-sdram-verilog
.....................\readme_sdr_sdram.txt
.....................\sdr_sdram.pdf
.....................\.imulation\sdr_sdram_tb.v
.....................\.ource\altclklock.v
.....................\......\Command.v
.....................\......\compile_all.v
.....................\......\control_interface.v
.....................\......\Params.v
.....................\......\PLL1.v
.....................\......\sdr_data_path.v
.....................\......\sdr_sdram.v
.....................\本参考设计学习总结.doc
.....................\doc
.....................\simulation
.....................\source
ref-sdr-sdram-verilog