文件名称:ref-sdr-sdram-verilog
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SDRAM的vegilog代码，做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM
相关搜索： sdram
SDRAM
verilog
VERILOG
SDRAM
verilog
SDR
SRAM
params
v
sdr
sdram
ref-sdr-sdram-vhdl
SDRAM
FIFO
SDRAM
verilog
VERILOG
SDRAM
verilog
SDR
SRAM
params
v
sdr
sdram
ref-sdr-sdram-vhdl
SDRAM
FIFO
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ref-sdr-sdram-verilog
.....................\doc
.....................\readme_sdr_sdram.txt
.....................\sdr_sdram.pdf
.....................\simulation
.....................\..........\sdr_sdram_tb.v
.....................\source
.....................\......\altclklock.v
.....................\......\Command.v
.....................\......\compile_all.v
.....................\......\control_interface.v
.....................\......\Params.v
.....................\......\PLL1.v
.....................\......\sdr_data_path.v
.....................\......\sdr_sdram.v
.....................\doc
.....................\readme_sdr_sdram.txt
.....................\sdr_sdram.pdf
.....................\simulation
.....................\..........\sdr_sdram_tb.v
.....................\source
.....................\......\altclklock.v
.....................\......\Command.v
.....................\......\compile_all.v
.....................\......\control_interface.v
.....................\......\Params.v
.....................\......\PLL1.v
.....................\......\sdr_data_path.v
.....................\......\sdr_sdram.v