文件名称:ref-sdr-sdram-vhdl
介绍说明--下载内容均来自于网络,请自行研究使用
DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
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(系统自动生成,下载前可以参看下载内容)
下载文件列表
CVS
doc
...\CVS
readme_sdr_sdram.txt
sdr_sdram.pdf
simulation
..........\CVS
..........\sdr_sdram_tb.vhd
source
......\Command.vhd
......\control_interface.vhd
......\CVS
......\pll1.vhd
......\sdr_data_path.vhd
......\sdr_sdram.vhd
doc
...\CVS
readme_sdr_sdram.txt
sdr_sdram.pdf
simulation
..........\CVS
..........\sdr_sdram_tb.vhd
source
......\Command.vhd
......\control_interface.vhd
......\CVS
......\pll1.vhd
......\sdr_data_path.vhd
......\sdr_sdram.vhd