资源列表
[VHDL编程] tut_timing_verilog
说明:Verilog source code is usually typed into one or more text files on a computer. Those text files are then submitted to a Verilog compiler or interpreter which builds the data files necessary for simulation or synth<Nguyen Chi Nhan> 在 2025-02-03 上传 | 大小:361kb | 下载:0
[VHDL编程] Verilog_VHDL_Golden_Reference_Guide
说明:Verilog source code is usually typed into one or more text files on a computer. Those text files are then submitted to a Verilog compiler or interpreter which builds the data files necessary for simulation or synth<Nguyen Chi Nhan> 在 2025-02-03 上传 | 大小:272kb | 下载:0
[VHDL编程] Crack_Altera_Quartus61.0-9.1
说明:Crack_Altera_Quartus61.0-9.1.rar license-Crack_Altera_Quartus61.0-9.1.rar license!!!<guobo> 在 2025-02-03 上传 | 大小:257kb | 下载:0
[VHDL编程] simple_pic
说明:一个通用中断系统的Verilog HDL描述,对想了解知道是怎么实现的读者,可以查看综合出来的电路,会有很大帮助!-A common interrupt system of the Verilog HDL descr iption of the would like to know how to achieve the readers know, there will be of great help!<陈永恒> 在 2025-02-03 上传 | 大小:436kb | 下载:0
[VHDL编程] irq_decoder
说明:中断优先编码器的描述,输出中断向量供CPU读取,非常好用,只要稍稍修改,就可以产生您所需要的中断向量。-Descr iption of interrupt priority encoder, the output for the CPU interrupt vector read, very easy to use, if slightly modified, it can generate interrupt vector you n<陈永恒> 在 2025-02-03 上传 | 大小:219kb | 下载:0
[VHDL编程] oscillograph
说明:用VHDL编写的oscillograph数字部分源代码,在Altera FPGA上跑通。直接把模拟部分输入输出AD,DA信号接入本模块即可。-Digital oscillograph with the written part of the VHDL source code, in the Altera FPGA on the run-pass. Directly to the analog input and output AD, D<蓝晶> 在 2025-02-03 上传 | 大小:14kb | 下载:0
[VHDL编程] frame_synchronization
说明:检测巴克码实现帧同步传输,vhdl语言,帧头-Detection of Barker code transmission to achieve fr a me synchronization<chenke> 在 2025-02-03 上传 | 大小:432kb | 下载:0