资源列表
[VHDL编程] simple_test
说明:This a vhdl code for colour converter fpga code for testing shape_gen code-This is a vhdl code for colour converter fpga code for testing shape_gen code<usha> 在 2025-01-26 上传 | 大小:1kb | 下载:0
[VHDL编程] wr_rd_all_registers_test
说明:This a vhdl code for colour converter fpga code for testing write and read transfers code-This is a vhdl code for colour converter fpga code for testing write and read transfers code<usha> 在 2025-01-26 上传 | 大小:1kb | 下载:0
[VHDL编程] intf_wrapper
说明:This a vhdl code for router code for testing write and read transfers code-This is a vhdl code for router code for testing write and read transfers code<usha> 在 2025-01-26 上传 | 大小:1kb | 下载:0
[VHDL编程] divisor_frecuencia
说明:its a divider clock. its possible select the frequency based in a master clock<edgar> 在 2025-01-26 上传 | 大小:1kb | 下载:0
[VHDL编程] music
说明:用Verilog HDL编写的音乐彩灯程序-Music Lantern program written using Verilog HDL<wenyangzeng> 在 2025-01-26 上传 | 大小:1kb | 下载:0
[VHDL编程] make-file-vcs.tar
说明:this the verilog code of 4:1 mux and i have used case statement to explain the logic of this mux-this is the verilog code of 4:1 mux and i have used case statement to explain the logic of this mux<mahavir> 在 2025-01-26 上传 | 大小:1kb | 下载:0
[VHDL编程] SFIFO_8960
说明:异步FIFO设计,简单适用,非常好用,节省资源。-Applicable asynchronous FIFO<liqiru> 在 2025-01-26 上传 | 大小:1kb | 下载:0
[VHDL编程] preambledeassemble
说明:its useful for dissembler data from continuous stream of transmitter data stream<kishan patel> 在 2025-01-26 上传 | 大小:1kb | 下载:0