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[VHDL编程] 16-bit-A-DCa16-bit-DAC-VHDL
说明:16-bit Analogue to Digital Converter&16-bit Digital to Analogue Converter VHDL source code.在modelsim下仿真通过-16-bit Analogue to Digital Converter & 16-bit Digital to Analogue Converter VHDL source code. Simulated in m<fangshan> 在 2024-10-08 上传 | 大小:1024 | 下载:0
[VHDL编程] 2-to-4-Decoder-with--Configuration
说明:2-to-4 Decoder with Testbench and Configuration This set of design units illustrates several features of the VHDL language including: Using generics to pass time delay values to design entities. Design hierarchy u<fangshan> 在 2024-10-08 上传 | 大小:1024 | 下载:0
[VHDL编程] divider-code
说明:本文档为FPGA的开发程序,用verilog语言实现了出发操作,欢迎参考。-This document is a the FPGA development program, verilog language starting operation, welcomed the reference.<秦艳召> 在 2024-10-08 上传 | 大小:1024 | 下载:0
[VHDL编程] Chinese_music_play
说明:基于FPGA实现开发的中国古曲《高山流水》蜂鸣音乐,采用verilog实现。-" Mountain and Flowing Water" beep music based on the classic Chinese music FPGA implementation developed using verilog achieve.<小梦> 在 2024-10-08 上传 | 大小:1024 | 下载:1
[VHDL编程] Autoseller_verilog
说明:基于FPGA实现的自动售货机,采用verilog语言实现-Vending machines based on FPGA verilog language<小梦> 在 2024-10-08 上传 | 大小:1024 | 下载:0
[VHDL编程] HalfbandDec
说明:基于FPGA开发的11阶半带升余弦FIR滤波器,用在阅读器基带滤波时的抽取滤波器使用,采用verilog语言实现。-Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.<小梦> 在 2024-10-08 上传 | 大小:1024 | 下载:0