资源列表
[VHDL编程] jk-filpflop
说明:这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的-This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met<zhangzicong> 在 2025-01-16 上传 | 大小:2kb | 下载:0
[VHDL编程] Common-multiplier-design
说明:常用乘法器设计,用FPGA能实现,值得下载。-Common multiplier design, FPGA can achieve, it is worth downloading.<吴敏> 在 2025-01-16 上传 | 大小:2kb | 下载:0
[VHDL编程] encode_8B10B
说明:用verilog编写的8B/10B编码模块。参考了网上的源码,并取消了时序,以纯逻辑实现。将3B/4B、5B/6B两部分单独写成模块,可读性更强-Using verilog 8B/10B encoding module. Online reference source, and canceled the timing, pure logic implementation. The 3B/4B, 5B/6B written two sep<Lang> 在 2025-01-16 上传 | 大小:2kb | 下载:0
[VHDL编程] IS61WV51232BLL
说明:这是SRAM-IS61WV51232BLL在NIOS软核应用下的读写时许代码。-This is SRAM-IS61WV51232BLL under NIOS soft-core application code reader o' clock.<谭松清> 在 2025-01-16 上传 | 大小:2kb | 下载:0
[VHDL编程] 232315digitalPLL
说明:vhdl matlab ...............simulink c++........ probgramme<said> 在 2025-01-16 上传 | 大小:2kb | 下载:0
[VHDL编程] ds1302_drive_program
说明:基于Verilog hdl的ds1302芯片的驱动程序-Ds1302 chip driver programme based on Verilog HDL.<刘邦> 在 2025-01-16 上传 | 大小:2kb | 下载:0
[VHDL编程] 16FFTverilog
说明: Hello, i have uploaded some interesting files - Hello, i have uploaded some interesting files ...<viet> 在 2025-01-16 上传 | 大小:2kb | 下载:0