资源列表
[VHDL编程] fen-V6.4
说明:Complete HMM-based speech recognition system, Matching Pursuit and orthogonal matching pursuit, Chaos indicator for Lyapunov index calculation.<bingnunneng > 在 2025-02-06 上传 | 大小:9kb | 下载:0
[VHDL编程] bv617
说明:Own five modulation signal, Mathematics is part of the subspace, Multivariate least squares fitting method of nonlinear equations.<faogiumaobun > 在 2025-02-06 上传 | 大小:9kb | 下载:0
[VHDL编程] icivd
说明:Acquisition and Processing of the speech signal, digital signal processing class-based, Various resource allocation algorithm, Jacobi iteration for solving linear equations class-based.<faogiumaobun > 在 2025-02-06 上传 | 大小:9kb | 下载:0
[VHDL编程] cdivn
说明:EULER numerical analysis method, Continuous phase modulation signal (CPM) to produce, It comprises aircraft flight attitude control, such as slip angle, tilt angle, roll angle, pitch angle.<jengfanjun > 在 2025-02-06 上传 | 大小:9kb | 下载:0
[VHDL编程] vp157
说明:Multirate signal processing, Sampling from a priori probability, calculate the weight, Is a practical method of path planning.<jengfanjun > 在 2025-02-06 上传 | 大小:9kb | 下载:0
[VHDL编程] TX_IP_Source
说明:串口发送ip核,配合 nios 使用,减少资源开支。(uart transmit TX_IP_Source)<haohmf > 在 2025-02-06 上传 | 大小:9kb | 下载:0
[VHDL编程] eetop.cn_GPIO
说明:通用的GPIO coding,Verilog编码(GPIO coding wrote by Verilog)<jackey527 > 在 2025-02-06 上传 | 大小:9kb | 下载:0
[VHDL编程] eetop.cn_uart 源码 (Verilog)
说明:Verilog编写的UART通信模块,比较清晰(UART model wrote by Verilog)<jackey527 > 在 2025-02-06 上传 | 大小:9kb | 下载:0
[VHDL编程] uart_latest.tar
说明:UART的VHDL建模代码,是一个标准的IP核(UART's VHDL modeling code is a standard IP core)<scenic_lee > 在 2025-02-06 上传 | 大小:9kb | 下载:0