资源列表

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[VHDL编程fen-V6.4

说明:Complete HMM-based speech recognition system, Matching Pursuit and orthogonal matching pursuit, Chaos indicator for Lyapunov index calculation.
<bingnunneng > 在 2025-02-06 上传 | 大小:9kb | 下载:0

[VHDL编程aa041

说明:Matlab wavelet analysis on complex, Suppressed carrier type differential phase modulation, Calculate the multifractal trend fluctuation analysis.
<loupoufun > 在 2025-02-06 上传 | 大小:9kb | 下载:0

[VHDL编程8647

说明:Do Vision Measurement PC code, Partially achieved tracking speed iterative relaxation algorithm, K-means clustering algorithm based on the PSO.
<loupoufun > 在 2025-02-06 上传 | 大小:9kb | 下载:0

[VHDL编程bv617

说明:Own five modulation signal, Mathematics is part of the subspace, Multivariate least squares fitting method of nonlinear equations.
<faogiumaobun > 在 2025-02-06 上传 | 大小:9kb | 下载:0

[VHDL编程icivd

说明:Acquisition and Processing of the speech signal, digital signal processing class-based, Various resource allocation algorithm, Jacobi iteration for solving linear equations class-based.
<faogiumaobun > 在 2025-02-06 上传 | 大小:9kb | 下载:0

[VHDL编程cdivn

说明:EULER numerical analysis method, Continuous phase modulation signal (CPM) to produce, It comprises aircraft flight attitude control, such as slip angle, tilt angle, roll angle, pitch angle.
<jengfanjun > 在 2025-02-06 上传 | 大小:9kb | 下载:0

[VHDL编程vp157

说明:Multirate signal processing, Sampling from a priori probability, calculate the weight, Is a practical method of path planning.
<jengfanjun > 在 2025-02-06 上传 | 大小:9kb | 下载:0

[VHDL编程TX_IP_Source

说明:串口发送ip核,配合 nios 使用,减少资源开支。(uart transmit TX_IP_Source)
<haohmf > 在 2025-02-06 上传 | 大小:9kb | 下载:0

[VHDL编程eetop.cn_GPIO

说明:通用的GPIO coding,Verilog编码(GPIO coding wrote by Verilog)
<jackey527 > 在 2025-02-06 上传 | 大小:9kb | 下载:0

[VHDL编程eetop.cn_uart 源码 (Verilog)

说明:Verilog编写的UART通信模块,比较清晰(UART model wrote by Verilog)
<jackey527 > 在 2025-02-06 上传 | 大小:9kb | 下载:0

[VHDL编程bin2ascii

说明:Bin to ascii converter, with leading zeros. Room for improvement, remove the leading zeros.
<xenfranco > 在 2025-02-06 上传 | 大小:9kb | 下载:0

[VHDL编程uart_latest.tar

说明:UART的VHDL建模代码,是一个标准的IP核(UART's VHDL modeling code is a standard IP core)
<scenic_lee > 在 2025-02-06 上传 | 大小:9kb | 下载:0
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