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[VHDL编程] pipeline_lut_multiplier
说明:pipeline_lut_multiplier, 一个使用查找表实现的流水线乘法器,本程序使用verilog HDL language 语言编写-pipeline_lut_multiplier ,a multiplier based on look up tablets ,and it is programing in verilog language<谷雨> 在 2025-02-09 上传 | 大小:5kb | 下载:0
[VHDL编程] sorter_block
说明:this is a code for a sorter block. read data a RAM and sort them. then write data in RAM-this is a code for a sorter block. read data a RAM and sort them. then write data in RAM<mohsen> 在 2025-02-09 上传 | 大小:5kb | 下载:0
[VHDL编程] VHDL_Multiplier
说明:三种 VHDL 实现乘法器的方法,可以用于学习FPGA的时序、组合电路,同时附带了 TestBench 程序-Three kinds of methods to achieve multiplier in VHDL, with TestBench<李成> 在 2025-02-09 上传 | 大小:5kb | 下载:0
[VHDL编程] mdio_slave_interface
说明:Management Data Input/Output Interfaces, or MDIO, are specified in the IEEE 802.3 standard. Their primary application is to provide a Serial Management Interface (SMI) to transfer management data between an Ethernet Me<sherry> 在 2025-02-09 上传 | 大小:5kb | 下载:0