[VHDL编程] SEG_CLOCK

说明：seg clk seg clk seg clk-seg clkseg clkseg clkseg clkseg clk
<yunU> 在 2025-04-23 上传 | 大小：1kb | 下载：0

[VHDL编程] CST_-_hokej

说明：VHDL school work. Display ice-hockey scores and time on 7seg display.
<thomas810> 在 2025-04-23 上传 | 大小：801kb | 下载：0

[VHDL编程] CST_-_Smajlici

说明：VHDL school work. Display four smiles on 8x8 matrix display. It use four button to :--VHDL school work. Display four smiles on 8x8 matrix display. It use four button to :-))
<thomas810> 在 2025-04-23 上传 | 大小：475kb | 下载：0

[VHDL编程] alphabeta_transform

说明：alpha beta transformation, for FPGA synthesis and implementation
<wahib> 在 2025-04-23 上传 | 大小：1kb | 下载：0

[VHDL编程] ROM

说明：FPGArom的IP核使用及仿真,Verilog语言，非常详细-IP core and use of simulation FPGArom, Verilog language, very detailed
<杨福廷> 在 2025-04-23 上传 | 大小：5.67mb | 下载：0

[VHDL编程] Filter_Convolution_Example

说明：Example of a convolution filter implemented in Vivado HLS, the high level synthesis tool Xilinx-Example of a convolution filter implemented in Vivado HLS, the high level synthesis tool Xilinx
<rickyalbert> 在 2025-04-23 上传 | 大小：1kb | 下载：0

[VHDL编程] synd

说明：Syndrome calculator basic unit for reed solomon decoder in verilog language
<humberto> 在 2025-04-23 上传 | 大小：1kb | 下载：0

[VHDL编程] behavioral-hmwk5

说明：Design a synchronous circuit which monitors a 3-bit code as the input. If the code has a constant value in four consecutive clock cycles, a flag is activated.
<mafa87> 在 2025-04-23 上传 | 大小：1kb | 下载：0

[VHDL编程] code

说明：Design the logic required for a “Dancing Light” system including 5 lights which are turned on repeatedly
<mafa87> 在 2025-04-23 上传 | 大小：1kb | 下载：0

[VHDL编程] code-hmwk7

说明：Make the required flag signals using the input clock signal (clk) and input flag (TKN). Whenever the TKN signal is activated, a sequence of activation of flag signals should be performed based on the timing diagram
<mafa87> 在 2025-04-23 上传 | 大小：1kb | 下载：0

[VHDL编程] hmwk3try.vhd

说明：Design a circuit that take three N-Bit binary numbers as inputs and calculate the average of the largest number and the smallest number as the output. Note that the length of the input numbers should be defined varia
<mafa87> 在 2025-04-23 上传 | 大小：1kb | 下载：0

[VHDL编程] verilog_experiment

说明：关于verilog的数码管显示，简单的输入输出，流水灯-about verilog test in and out ,about light on and off
<孙炜荣> 在 2025-04-23 上传 | 大小：1.66mb | 下载：0