资源列表
[VHDL编程] DE2_115_Audio
说明:This a shared & storage file, which was written by Altera. It is quite possible that Applications will use this sample.-This is a shared & storage file, which was written by Altera. It is quite possible that Applications<lizhi> 在 2025-04-08 上传 | 大小:1.82mb | 下载:0
[VHDL编程] DE2_115_TV
说明:This an application of FPGA which wrote by Altera. It can be used for interfacing VGA, SDRAM on DE2-115-This is an application of FPGA which wrote by Altera. It can be used for interfacing VGA, SDRAM on DE2-115<lizhi> 在 2025-04-08 上传 | 大小:9.67mb | 下载:0
[VHDL编程] double_closed_loop
说明:本程序是基于zynq_7000的FPGA的一个同步电机控制的平台,verilog语言-based on zynq_7000 fpga-MOTOR CONTROL<葛明明> 在 2025-04-08 上传 | 大小:193kb | 下载:0
[VHDL编程] RS-encoder
说明:RSC encoder in VHDL. Hope it helpful.<thang> 在 2025-04-08 上传 | 大小:4kb | 下载:0
[VHDL编程] or1200.tar
说明:OpenRISC 1200 cpu with integrated patches to support ORPSOC and FuseSOC builders<corgano> 在 2025-04-08 上传 | 大小:3.52mb | 下载:0
[VHDL编程] verilog-arbiter.tar
说明:Verilog arbitrator for Wishbone R3 compliant bus<corgano> 在 2025-04-08 上传 | 大小:5kb | 下载:0
[VHDL编程] wb_sdram_ctrl.tar
说明:Generic Wishbone R3 compliant SDRAM controller written in Verilog<corgano> 在 2025-04-08 上传 | 大小:10kb | 下载:0
[VHDL编程] bt656_timing_analysis
说明:BT656信号分析参考规格书,对分析bt656信号非常有帮助-The video standard ITU-R.656 timing analysis<zbunix> 在 2025-04-08 上传 | 大小:81kb | 下载:0
[VHDL编程] Basys2Lcd
说明:This the file of controling a LCD display of Basys2 board used to pass the exams of VHDL-This is the file of controling a LCD display of Basys2 board used to pass the exams of VHDL<plaukuotis> 在 2025-04-08 上传 | 大小:1kb | 下载:0