资源列表
[VHDL编程] rtc_interface
说明:该段代码给移植到黑金DB2C5开发板上面的RTC接口verilog代码,已经经过实验验证。-This code to transplant to black gold DB2C5 development board above RTC interface verilog code, has been experimentally validated.<杨杨> 在 2025-02-03 上传 | 大小:1.83mb | 下载:0
[VHDL编程] Experiment23
说明:该段代码给移植到黑金DB2C5开发板上面的数码管及RTC系统verilog代码,已经经过实验验证。-The sections of the code to be ported to the digital tube the black gold DB2C5 development board above and RTC System Verilog code has been experimentally validated.<杨杨> 在 2025-02-03 上传 | 大小:2.59mb | 下载:0
[VHDL编程] vga_interface_demo
说明:该段代码给移植到黑金DB2C5开发板上面的VGA显示verilog代码,已经经过实验验证。-This section of code to be ported to the black gold DB2C5 development board above VGA display Verilog code, has been experimentally validated.<杨杨> 在 2025-02-03 上传 | 大小:81kb | 下载:0
[VHDL编程] ddr_data_path
说明:sdram数据路径模块编程,经综合后壳生成rtl级电路图-SDRAM data path module shell programming, after comprehensive RTL-level circuit diagram is generated<xiaojie> 在 2025-02-03 上传 | 大小:2kb | 下载:0
[VHDL编程] ep1c6_14_song
说明:关于歌曲的小程序,适合于VHDL基础学习,欢迎大家下载。-Small program on the song, suitable for the VHDL-based learning, welcome to download.<川虎> 在 2025-02-03 上传 | 大小:66kb | 下载:0
[VHDL编程] ep1c6_15_clock
说明:基于FPGA的数字时钟,可实现自动计时,秒表等功能,适合于基础学习,欢迎大家下载-FPGA-based digital clock, automatic chronograph, stopwatch function, suitable for basic learning, welcome to download<川虎> 在 2025-02-03 上传 | 大小:76kb | 下载:0
[VHDL编程] ep1c6_3_keyled
说明:关于FPGA的基础学习,按键控制模块,欢迎大家下载。-FPGA-based learning, the key control module, welcome to download.<川虎> 在 2025-02-03 上传 | 大小:34kb | 下载:0
[VHDL编程] ep1c6_11_freqtest
说明:十进制计数器,以及数码管显示模块,属于FPGA基础学习,欢迎大家下载-Decimal counter, as well as the digital display module belonging to the FPGA-based learning are welcome to download<川虎> 在 2025-02-03 上传 | 大小:72kb | 下载:0
[VHDL编程] ep1c6_24_step_moto
说明:使用PWM方法来控制步进电机细分旋转,属于基础学习的小实验程序代码,欢迎大家下载。-PWM method is used to control the stepper motor rotation segments are based learning small experimental procedure code, welcome to download.<川虎> 在 2025-02-03 上传 | 大小:52kb | 下载:0
[VHDL编程] DDS_SYS_CLK100M
说明:基于FPGA的信号源设计,100M时钟,32位相位累加,能产生正玄波、方波,三角波,锯齿波,频率可调,频率范围0.03HZ-15MHZ。-FPGA-based signal source design, 100M clock, 32-bit phase accumulation can produce sine wave, square wave, triangle wave, sawtooth, adjustable frequenc<zhangchuan> 在 2025-02-03 上传 | 大小:2.61mb | 下载:0