文件名称:DDR_SDRAM_Controller
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DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
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下载文件列表
rd1020_DDR SDRAM Controller
...........................\DDR SDRAM Controller.files
...........................\..........................\arrow.gif
...........................\..........................\arrow1.gif
...........................\..........................\diskette.gif
...........................\..........................\external.css
...........................\..........................\go.gif
...........................\..........................\header.gif
...........................\..........................\make_agent_emb.jpg
...........................\..........................\pdfmid.gif
...........................\..........................\ref_design_logo.gif
...........................\..........................\spacer.gif
...........................\DDR SDRAM Controller.htm
...........................\rd1020.pdf
...........................\source
...........................\......\ddr_ctrl.v
...........................\......\ddr_data.v
...........................\......\ddr_par.v
...........................\......\ddr_pll_orca.v
...........................\......\ddr_pll_orca_sp.v
...........................\......\ddr_sig.v
...........................\......\ddr_top.v
...........................\testbench
...........................\.........\ddr_tb.v
...........................\.........\stimulus.v
...........................\DDR SDRAM Controller.files
...........................\..........................\arrow.gif
...........................\..........................\arrow1.gif
...........................\..........................\diskette.gif
...........................\..........................\external.css
...........................\..........................\go.gif
...........................\..........................\header.gif
...........................\..........................\make_agent_emb.jpg
...........................\..........................\pdfmid.gif
...........................\..........................\ref_design_logo.gif
...........................\..........................\spacer.gif
...........................\DDR SDRAM Controller.htm
...........................\rd1020.pdf
...........................\source
...........................\......\ddr_ctrl.v
...........................\......\ddr_data.v
...........................\......\ddr_par.v
...........................\......\ddr_pll_orca.v
...........................\......\ddr_pll_orca_sp.v
...........................\......\ddr_sig.v
...........................\......\ddr_top.v
...........................\testbench
...........................\.........\ddr_tb.v
...........................\.........\stimulus.v