文件名称:ddr2_controller
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DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.
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下载文件列表
ddr2_controller\dcm_0.v
...............\ddr2_spartan3a1400abank1fg676.v
...............\ddr2_spartan3a1400abank1fg676_addr_gen_0.v
...............\ddr2_spartan3a1400abank1fg676_cal_ctl_0.v
...............\ddr2_spartan3a1400abank1fg676_cal_top.v
...............\ddr2_spartan3a1400abank1fg676_clk_dcm.v
...............\ddr2_spartan3a1400abank1fg676_cmd_fsm_0.v
...............\ddr2_spartan3a1400abank1fg676_cmp_data_0.v
...............\ddr2_spartan3a1400abank1fg676_controller_0.v
...............\ddr2_spartan3a1400abank1fg676_controller_iobs_0.v
...............\ddr2_spartan3a1400abank1fg676_data_path_0.v
...............\ddr2_spartan3a1400abank1fg676_data_path_iobs_0.v
...............\ddr2_spartan3a1400abank1fg676_data_read_0.v
...............\ddr2_spartan3a1400abank1fg676_data_read_controller_0.v
...............\ddr2_spartan3a1400abank1fg676_data_write_0.v
...............\ddr2_spartan3a1400abank1fg676_dqs_delay.v
...............\ddr2_spartan3a1400abank1fg676_fifo_0_wr_en_0.v
...............\ddr2_spartan3a1400abank1fg676_fifo_1_wr_en_0.v
...............\ddr2_spartan3a1400abank1fg676_infrastructure.v
...............\ddr2_spartan3a1400abank1fg676_infrastructure_iobs_0.v
...............\ddr2_spartan3a1400abank1fg676_infrastructure_top_0.v
...............\ddr2_spartan3a1400abank1fg676_iobs_0.v
...............\ddr2_spartan3a1400abank1fg676_lfsr32_0.v
...............\ddr2_spartan3a1400abank1fg676_main_0.v
...............\ddr2_spartan3a1400abank1fg676_parameters_0.v
...............\ddr2_spartan3a1400abank1fg676_ram8d_0.v
...............\ddr2_spartan3a1400abank1fg676_rd_gray_cntr.v
...............\ddr2_spartan3a1400abank1fg676_s3_dm_iob_0.v
...............\ddr2_spartan3a1400abank1fg676_s3_dqs_iob.v
...............\ddr2_spartan3a1400abank1fg676_s3_dq_iob.v
...............\ddr2_spartan3a1400abank1fg676_tap_dly.v
...............\ddr2_spartan3a1400abank1fg676_test_bench_0.v
...............\ddr2_spartan3a1400abank1fg676_top_0.v
...............\ddr2_spartan3a1400abank1fg676_wr_gray_cntr.v
...............\ddr2_top.ucf
...............\ddr2_top.v
ddr2_controller
...............\ddr2_spartan3a1400abank1fg676.v
...............\ddr2_spartan3a1400abank1fg676_addr_gen_0.v
...............\ddr2_spartan3a1400abank1fg676_cal_ctl_0.v
...............\ddr2_spartan3a1400abank1fg676_cal_top.v
...............\ddr2_spartan3a1400abank1fg676_clk_dcm.v
...............\ddr2_spartan3a1400abank1fg676_cmd_fsm_0.v
...............\ddr2_spartan3a1400abank1fg676_cmp_data_0.v
...............\ddr2_spartan3a1400abank1fg676_controller_0.v
...............\ddr2_spartan3a1400abank1fg676_controller_iobs_0.v
...............\ddr2_spartan3a1400abank1fg676_data_path_0.v
...............\ddr2_spartan3a1400abank1fg676_data_path_iobs_0.v
...............\ddr2_spartan3a1400abank1fg676_data_read_0.v
...............\ddr2_spartan3a1400abank1fg676_data_read_controller_0.v
...............\ddr2_spartan3a1400abank1fg676_data_write_0.v
...............\ddr2_spartan3a1400abank1fg676_dqs_delay.v
...............\ddr2_spartan3a1400abank1fg676_fifo_0_wr_en_0.v
...............\ddr2_spartan3a1400abank1fg676_fifo_1_wr_en_0.v
...............\ddr2_spartan3a1400abank1fg676_infrastructure.v
...............\ddr2_spartan3a1400abank1fg676_infrastructure_iobs_0.v
...............\ddr2_spartan3a1400abank1fg676_infrastructure_top_0.v
...............\ddr2_spartan3a1400abank1fg676_iobs_0.v
...............\ddr2_spartan3a1400abank1fg676_lfsr32_0.v
...............\ddr2_spartan3a1400abank1fg676_main_0.v
...............\ddr2_spartan3a1400abank1fg676_parameters_0.v
...............\ddr2_spartan3a1400abank1fg676_ram8d_0.v
...............\ddr2_spartan3a1400abank1fg676_rd_gray_cntr.v
...............\ddr2_spartan3a1400abank1fg676_s3_dm_iob_0.v
...............\ddr2_spartan3a1400abank1fg676_s3_dqs_iob.v
...............\ddr2_spartan3a1400abank1fg676_s3_dq_iob.v
...............\ddr2_spartan3a1400abank1fg676_tap_dly.v
...............\ddr2_spartan3a1400abank1fg676_test_bench_0.v
...............\ddr2_spartan3a1400abank1fg676_top_0.v
...............\ddr2_spartan3a1400abank1fg676_wr_gray_cntr.v
...............\ddr2_top.ucf
...............\ddr2_top.v
ddr2_controller