说明:计时实现led和数码管的闪亮,模拟交通红绿黄灯的状态,led代表交通灯,数码管倒计时-Timing and realization led digital tube shiny, red, green yellow simulated traffic state, led on behalf of traffic lights, LED countdown <zhuwen> 在 2025-02-07 上传
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说明:FPGA的IP核中除法算法的源代码,是Verilog语言的,易于初学者的学习。-FPGA IP core in the division algorithm source code, Verilog language, easy for beginners to learn. <leeyoung> 在 2025-02-07 上传
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