资源列表
[VHDL编程] LATTICE_synplifyPro_basic_flow
说明:LATTICE 同步( synplifyPro)basic_flow 源码-LATTICE synchronization (synplifyPro) basic_flow source<zengwenbo> 在 2025-02-07 上传 | 大小:7kb | 下载:0
[VHDL编程] piplelinecpu
说明:流水线CPU,实现MIPS简单指令的运行,在XLINX实验板上运行-Pipelined CPU, MIPS simple instructions to achieve the operation, run in XLINX experimental board<谢志鹏> 在 2025-02-07 上传 | 大小:5.47mb | 下载:0
[VHDL编程] MultiplierHDL_FPGA
说明:Implementation of 4 bit array multiplier using Verilog HDL<sandeep> 在 2025-02-07 上传 | 大小:1.39mb | 下载:0
[VHDL编程] gaus_filter
说明:This Gaussian filter is implemented by Verilog HDL and successfully simulated on ModelSim. Besides, it has been implemented on Altera DE2-70 board<Gam> 在 2025-02-07 上传 | 大小:5kb | 下载:0
[VHDL编程] tiling_multi_channel
说明:This the Tiling multichannel module which used in the JPEG2000 encoder. This module uses the replicated method for boundary extension.-This is the Tiling multichannel module which used in the JPEG2000 encoder. This modul<Gam> 在 2025-02-07 上传 | 大小:15kb | 下载:0