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[VHDL编程reciever

说明:通过VHDL语言编写关于8位数码管的8位数据接收器程序。-failed to translate
<LS > 在 2025-03-02 上传 | 大小:1kb | 下载:0

[VHDL编程FPGA-Prototyping-

说明:Wiley-Interscience - FPGA Prototyping by Verilog Examples - book-Wiley-Interscience- FPGA Prototyping by Verilog Examples- Jun 2008.pdf
<key> 在 2025-03-02 上传 | 大小:16.3mb | 下载:0

[VHDL编程VGA2

说明:VGA controller initialy designed for altera DE2 FPGA with 10 bits DAC. probably works with other systems if you have the correct clock source.
<alzemiro> 在 2025-03-02 上传 | 大小:2kb | 下载:0

[VHDL编程vhdl_verilog_tutorial

说明:Verilog and Verilog tutorial, very good for begginers
<alzemiro> 在 2025-03-02 上传 | 大小:2kb | 下载:0

[VHDL编程tutorial

说明:another verilog VHDL tutorial, targeting altera DE2 board, but very intuituve.
<alzemiro> 在 2025-03-02 上传 | 大小:15kb | 下载:0

[VHDL编程fir

说明:FIR filter example for FPGA development
<alzemiro> 在 2025-03-02 上传 | 大小:11kb | 下载:0

[VHDL编程DE2_Default

说明:Altera DE2 demonstration design, lot of interesting verilog code for synthesis
<alzemiro> 在 2025-03-02 上传 | 大小:4.87mb | 下载:0

[VHDL编程FPGAtomcs51

说明:FPGA与51单片机通信接口电路工程文件,非常好用,对于学习VHDL语言的同学们帮助很大。-FPGA and MCU communication interface circuit 51 project files, very easy to use, for students to learn VHDL language of great help.
<math> 在 2025-03-02 上传 | 大小:421kb | 下载:0

[VHDL编程FPGA-FIR

说明:FIR滤波器,算法,采用VHDL编程语言,算法比较简单,希望对大家有所帮助。-FIR filter algorithm, using VHDL programming language, the algorithm is simple, we want to help.
<math> 在 2025-03-02 上传 | 大小:1.13mb | 下载:0

[VHDL编程FPGAzigzag

说明:三角波发生器,VHDL语言描述,通过信号分频等实现波形发生,已经在示波器上验证了,效果不过。-Triangular wave generator, VHDL language descr iption, such as through the realization of the signal waveform frequency has been verified on an oscilloscope, the effect, how
<math> 在 2025-03-02 上传 | 大小:46kb | 下载:0

[VHDL编程ISE-anzhuangjiaocheng

说明:ISE安装详细说明,包括工程开发流程,测试文件编辑等,包括大量截图,非常适合初学着。-ISE installation details, including engineering processes, testing, editing documents, including a large number of shots, is very suitable for beginners with.
<math> 在 2025-03-02 上传 | 大小:1.81mb | 下载:0

[VHDL编程SRAM_1wait

说明:The aim of this vhdl file is to create a simple interface betwhen the sram and a basic processor on a semisync data bus. This was made using the test board DE2 from Altera.
<Hz> 在 2025-03-02 上传 | 大小:1kb | 下载:0
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