资源列表
[VHDL编程] Melay_1001
说明：it is Mealy model s vhdl code. and it was implemented and run in Altera quarts - -it is Mealy model s vhdl code. and it was implemented and run in Altera quarts - II<Henal patel> 在 2025-02-14 上传 | 大小：24kb | 下载：0
[VHDL编程] Frequency_Div
说明：it is vhdl code for "frequency divider" which was implemented and run in altera quarts- -it is vhdl code for "frequency divider" which was implemented and run in altera quarts- II<Henal patel> 在 2025-02-14 上传 | 大小：24kb | 下载：0
[VHDL编程] digital-lock
说明：数字锁的详细设计流程以及VHDL仿真过程和结果，附有源码-The detailed design process digital lock and VHDL simulation process and results, with source code<WPQ> 在 2025-02-14 上传 | 大小：24kb | 下载：0
[VHDL编程] Half_Frequence
说明：本程序基于VHDL语言，设计分频器，其中包含半整数分频占空比不为50 奇数分频占空比为50 任意小数分频 -The program is based on VHDL language design divider, which includes half-integer divider 50 duty cycle is not odd frequency 50 duty cycle any fractional<qikaiyi> 在 2025-02-14 上传 | 大小：24kb | 下载：0
[VHDL编程] I2S_3
说明：that is another I2S code example<fatih mercimek> 在 2025-02-14 上传 | 大小：24kb | 下载：0
[VHDL编程] I2S_6
说明：CLK example is existing at that file<fatih mercimek> 在 2025-02-14 上传 | 大小：24kb | 下载：0
[VHDL编程] Verilog-example2
说明：verilog 实例讲解第二部分，进一步拓展对基础知识的应用，通过实例分析帮助大家理解verilog-verilog examples to explain the second part, to further expand on the basics of the application, by an example to help you understand verilog<lyon> 在 2025-02-14 上传 | 大小：24kb | 下载：0