[VHDL编程] uart_verilog

说明：简化的串口通信，去掉了奇偶校验位，波特率为9600，测试通过，fpga型号为xinlinx vp20-Simplified serial communication, removing the parity bit, the baud rate to 9600, test, fpga model xinlinx vp20
<刘红亮> 在 2025-02-08 上传 | 大小：5kb | 下载：0

[VHDL编程] DDS

说明：用51和 FPGA实现的 DDS的程序-FPGA with 51 and realize the process of DDS
<胡玉贵> 在 2025-02-08 上传 | 大小：5kb | 下载：0

[VHDL编程] mctrl

说明：不可多的的内存控制代码,是VHDL开发的珍贵参考资料!-Not much memory control code is developed in VHDL valuable reference!
<徐新风> 在 2025-02-08 上传 | 大小：5kb | 下载：0

[VHDL编程] SPI_Code(Verilog)

说明：SPI总线硬件描述语言Verilog下的实现，含主模式和从模式的实现，经过仿真验证，可作为一个单独的模块使用-SPI bus under the Verilog hardware descr iption language to achieve with the main mode and slave mode realization, through simulation, can be used as a separate modu
<高兵> 在 2025-02-08 上传 | 大小：5kb | 下载：0

[VHDL编程] LED_VHDL

说明：FPGA驱动LED静态显示以及FPGA驱动LED动态显示（4位）-FPGA-driven static LED display and LED driver FPGA dynamic display (4)
<wudi> 在 2025-02-08 上传 | 大小：5kb | 下载：0

[VHDL编程] LCD

说明：基于vhdl语言的LCD控制程序代码及仿真-Based on the VHDL language LCD control and simulation code
<hlj1232123> 在 2025-02-08 上传 | 大小：5kb | 下载：0

[VHDL编程] rs

说明：RS编码，verilog编写，可以自定义多项式，(255,233)和(204,188)均可。-RS coding, verilog prepared, can customize the polynomial, (255,233) and (204188) may.
<sunwind> 在 2025-02-08 上传 | 大小：5kb | 下载：0

[VHDL编程] adder4

说明：verilog加法器,附加测试文件 可用modelsim 仿真实现-Verilog Adder, additional test file ModelSim simulation can be used to achieve
<luminous> 在 2025-02-08 上传 | 大小：5kb | 下载：2

[VHDL编程] zyj

说明：包含了电子时钟的主要功能,输入CLK为1KHZ,输出为动态扫描8段CLD显示.有闹铃,正点报时,时间调整.调整时能够闪烁显示.本时钟为24小时制.课程设计优秀通过.运行平台:MAX+PLUS2.-Contains the main function of the electronic clock, input CLK for 1KHZ, output for the dynamic scan 8 CLD show. There are
<zyj> 在 2025-02-08 上传 | 大小：5kb | 下载：0

[VHDL编程] descode

说明：Encryption has become a part and parcel of our lives and we have accepted the fact that data is going to encrypted and decrypted at various stages. However, there is not a single encryption algorithm followed everywhere.
<akram> 在 2025-02-08 上传 | 大小：5kb | 下载：0

[VHDL编程] tcdg

说明：Encryption has become a part and parcel of our lives and we have accepted the fact that data is going to encrypted and decrypted at various stages. However, there is not a single encryption algorithm followed everywhere.
<akram> 在 2025-02-08 上传 | 大小：5kb | 下载：0

[VHDL编程] test-des

说明：Encryption has become a part and parcel of our lives and we have accepted the fact that data is going to encrypted and decrypted at various stages. However, there is not a single encryption algorithm followed everywhere.
<akram> 在 2025-02-08 上传 | 大小：5kb | 下载：0