[VHDL编程] gtx_drp

说明：高速串行设计FPGA-GTX IP设置生成drp模块，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接-High-speed serial design FPGA-GTX IP setting generation drp module, dynamically configurable rate 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link
<周召涛> 在 2025-02-02 上传 | 大小：2kb | 下载：0

[VHDL编程] controller

说明： Simple Microprocessor Design (ESD Book Chapter 3) Copyright 2001 Weijun Zhang Controller (control logic plus state register) VHDL FSM modeling- Simple Microprocessor Design (ESD Book Chapter 3) Copyrig
<mohamed> 在 2025-02-02 上传 | 大小：2kb | 下载：0

[VHDL编程] Controller(FSM)

说明： Simple Bridge (ESD book figure 2.14) by Weijun Zhang, 04/2001 RT level design using Controller(FSM) + DataPath- Simple Bridge (ESD book figure 2.14) by Weijun Zhang, 04/2001 RT level design using
<mohamed> 在 2025-02-02 上传 | 大小：2kb | 下载：0

[VHDL编程] GCD-CALCULATOR

说明： GCD CALCULATOR (ESD book figure 2.11) Weijun Zhang, 04/2001 we can put all the components in one document(gcd2.vhd) or put them in separate files this is the example of RT level modeling (FSM + DataP
<mohamed> 在 2025-02-02 上传 | 大小：2kb | 下载：0

[VHDL编程] scsa

说明：Speculative variable latency adders have attracted strong interest thanks to their capability to reduce average delay compared to traditional architectures. This proposes a novel variable latency speculative adder based
<preethi/charu> 在 2025-02-02 上传 | 大小：2kb | 下载：0

[VHDL编程] Segmentation-4G

说明：Segmentation of the 4G standard
<sherif> 在 2025-02-02 上传 | 大小：2kb | 下载：0

[VHDL编程] mealy_state_machine_v

说明：mealy状态机示例代码，可以在此代码上学期规范的状态机写法-mealy state machine sample code, this code can be on a state machine specification semester wording
<tiangang> 在 2025-02-02 上传 | 大小：2kb | 下载：0

[VHDL编程] moore_state_machine_v

说明：moor状态机的示例代码，再次基础上可以学习标准的状态机写法-moor state machine sample code, we can once again learning standards based on the wording of the state machine
<tiangang> 在 2025-02-02 上传 | 大小：2kb | 下载：0

[VHDL编程] user_encoded_machine_v

说明：The Verilog HDL Templates for State Machines that included in the Design Example web page are: o 4-State Mealy State Machine o 4-State Moore State Machine o Safe State Machine o User-Encoded State Machine-T
<tiangang> 在 2025-02-02 上传 | 大小：2kb | 下载：0

[VHDL编程] safe_state_machine_v

说明：The Verilog HDL Templates for State Machines that included in the Design Example web page are: o 4-State Mealy State Machine o 4-State Moore State Machine o Safe State Machine o User-Encoded State Machine-T
<tiangang> 在 2025-02-02 上传 | 大小：2kb | 下载：0

[VHDL编程] design

说明：浮点数是属于有理数中某特定子集的数的数字表示，在计算机中用以近似表示任意某个实数。-Floating point numbers are rational numbers belonging to a particular subset of the digital representation for an approximate representation of any real number in the computer.
<李长兴> 在 2025-02-02 上传 | 大小：2kb | 下载：0

[VHDL编程] lcd16x2_ctrl

说明：lcd16*2初始化源码，verilog 可直接引用-lcd16*2 initialization
<钟颖> 在 2025-02-02 上传 | 大小：2kb | 下载：0