资源列表
[VHDL编程] Altera_Device_Package_Information
说明:Altera 全部型号的FPGA及CPLD的配置指南,做PCB和FPGA开发人员参考较好-Altera all model FPGA and CPLD configuration guide, PCB and FPGA developer to do a better reference<xinmuwang> 在 2024-11-17 上传 | 大小:3.23mb | 下载:0
[VHDL编程] CPU-Project
说明:CPU设计,包含基本的指令集,能执行简单的程序。考虑了CPU,寄存器,存储器和指令集之间的关系。即读写寄存器,读写存储器和执行指令。-CPU design, including basic instruction set, to execute a simple program. Consider the CPU, registers, memory, and the relationship between instruction s<ilmf> 在 2024-11-17 上传 | 大小:3.23mb | 下载:0
[VHDL编程] clock_seg
说明:用FPGA分频,做一个有时分秒的时钟,并用数码管显示-FPGA divide a sometimes every minute clock, and digital display<mingzhanghui> 在 2024-11-17 上传 | 大小:3.22mb | 下载:0
[VHDL编程] clock_seg
说明:用FPGA分频,做一个有时分秒的时钟,并用数码管显示-FPGA divide a sometimes every minute clock, and digital display<mingzhanghui> 在 2024-11-17 上传 | 大小:3.22mb | 下载:0
[VHDL编程] uart
说明:用Verilog HDL,实现的FPGA串口调试程序,已经在硬件上调试成功-With Verilog HDL, FPGA serial debugger implemented in hardware debugging has been successful<ruanguopqing> 在 2024-11-17 上传 | 大小:3.23mb | 下载:0