资源列表
[VHDL编程] uart2bus_latest
说明:uart IP, including rx,tx module,and FSM control,data paser logic. including: testbench-uart IP<andrew.zhang> 在 2025-04-18 上传 | 大小:271kb | 下载:0
[VHDL编程] Verilog-master
说明:包含多个verilog源码,主要是AD7606的官方驱动,备注详细,学习参考。-Comprising a plurality of verilog source code, mainly AD7606 official driver, detailed notes, study reference.<Tao heng> 在 2025-04-18 上传 | 大小:28.26mb | 下载:0