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[VHDL编程] VHDL-Project
说明:Design of a Moore Synchronous Sequential Machine that operates according to the following two sequences.<Nandini> 在 2025-03-15 上传 | 大小:57kb | 下载:0
[VHDL编程] a2755985-cf79-4654-bc8e-c8eae1b49a2d
说明:特权同学的数字摄像头显示,东西很多,很值得学习-Privileged students digital camera show, a lot of things, it is worth learning<pz> 在 2025-03-15 上传 | 大小:1.5mb | 下载:0
[VHDL编程] NCVerilog_tutorial-chinese
说明:linux下cadence nc_verilog工具使用教程,中文的,很详细,很适合学习-tool under linux cadence nc_verilog tutorials, Chinese, very detailed, very suitable for learning<pz> 在 2025-03-15 上传 | 大小:577kb | 下载:0
[VHDL编程] clock-domain-crossinng.pdf.docx
说明:this source verilog code for clock domain crossing. -this is source verilog code for clock domain crossing.<rupesh> 在 2025-03-15 上传 | 大小:16kb | 下载:0