资源列表
[VHDL编程] RS232_kw_final
说明:A code to develop a communication link for RS232<Brian> 在 2025-03-16 上传 | 大小:1.78mb | 下载:0
[VHDL编程] Lab_intro2_ayjh
说明:A code to develop a cascade of counter<Brian> 在 2025-03-16 上传 | 大小:475kb | 下载:0
[VHDL编程] Video_ColorBar
说明:vhdl编写的程序,主要用来做彩条发生器,是CPLD开发的一个小例子而已,但是基础很重要嘛-vhdl programs written primarily used for color bar generator, is a small example of CPLD development only, but the basic thing is very important<> 在 2025-03-16 上传 | 大小:514kb | 下载:0
[VHDL编程] vhdl_codes
说明:this parallel to serial controller-this is parallel to serial controller<Heramb> 在 2025-03-16 上传 | 大小:7kb | 下载:0
[VHDL编程] a-vhdl-can-controller
说明:a vhdl can controller project using vhdl programmming language-a vhdl can controller project using vhdl programmming language..<Rahul> 在 2025-03-16 上传 | 大小:110kb | 下载:0
[VHDL编程] all-digital-fm-receiver
说明:all digital fm receiver using vhdl programming language project for electronics and communication engineering students.<Rahul> 在 2025-03-16 上传 | 大小:1.47mb | 下载:0
[VHDL编程] Design.Recipes.for.FPGAs.pdf
说明:Design Recipes for FPGAs (Peter Wilson) This book provides a rich toolbox of design techniques and templates to solve practical, every-day problems using FPGAs. Using a modular structure, the book gives easy-to-find de<ynona> 在 2025-03-16 上传 | 大小:1.36mb | 下载:0
[VHDL编程] Writing-Testbenches-using-System-Verilog.tar
说明:Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification<ynona> 在 2025-03-16 上传 | 大小:2.65mb | 下载:0
[VHDL编程] sdram_yadmc.tar
说明:/* * Yet Another Dynamic Memory Controller * Copyright (C) 2008 Sebastien Bourdeauducq - http://lekernel.net * This file is part of Milkymist. * * Milkymist is free software you can redistribute it and/or<shangdawei> 在 2025-03-16 上传 | 大小:21kb | 下载:0
[VHDL编程] sdram_vhd_134
说明:Design Descr iption: The SDRAM controller is designed for a Virtex device. It s simulated with Micron SDRAM models. The design is verified with backannotated simulation at 125MHz. For a full functional descr iption<shangdawei> 在 2025-03-16 上传 | 大小:398kb | 下载:0