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[VHDL编程] waveformgenerator
说明:The following information has been generated by Exemplar Logic -- and may be freely distributed and modified. -- -- Design name : smart_waveform -- -- Purpose : This design is a smart waveform generator. -Th<jgc> 在 2025-03-16 上传 | 大小:1kb | 下载:0
[VHDL编程] generadorfrecuencia
说明:Frecuenzy generator with the following in and out, Frecuencia : IN STD_LOGIC_VECTOR(3 DOWNTO 0) CLK : IN STD_LOGIC CLKOut : OUT STD_LOGIC-Frecuenzy generator with the following in and out, Frecuencia : IN<jgc> 在 2025-03-16 上传 | 大小:3kb | 下载:0
[VHDL编程] GeneradorFunciones
说明:Sine signal generator with the following I/O entity sinewave is port (clk :in std_logic dataout : out integer range -128 to 127 ) end sinewave -Sine signal generator with the following I/O entity si<jgc> 在 2025-03-16 上传 | 大小:1kb | 下载:0
[VHDL编程] Universal-Register
说明:Octal D-Type Register with 3-State Outputs -- Simple model of an Octal D-type register with three-state outputs using two concurrent statements.<jgc> 在 2025-03-16 上传 | 大小:1kb | 下载:0
[VHDL编程] Octal-D-Type-Register
说明:Octal D-Type Register with 3-State Outputs -- Simple model of an Octal D-type register with three-state outputs using two concurrent statements.<jgc> 在 2025-03-16 上传 | 大小:1kb | 下载:0
[VHDL编程] eetop.cn_Crack_Modelsim.SE.6.6
说明:Modelsim 6.6c keygen<王京> 在 2025-03-16 上传 | 大小:652kb | 下载:0