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[VHDL编程] keypadinterfacecontroller
说明:设计并实现一个4X8键盘接口控制器,含有时序产生电路、键盘扫描电路、弹跳消除电路、键盘译码电路、按键码存储电路、显示电路。要求:当按下某一键时,在数码管上显示该键对应的键值-Design and implement a 4X8 keypad interface controller, with timing generator circuit, the keyboard scanning circuit, bounce eliminat<zhuimeng> 在 2025-03-16 上传 | 大小:6kb | 下载:0
[VHDL编程] SystemVerilogAssertion
说明:SystemVerilog Assertion的应用例子。例子均在Synopsys VCS环境下编译通过。-The uploaded files are examples of Systemverilog Assertions. All of the codes are compiled successfully in Synopsys VCS environment.<ls> 在 2025-03-16 上传 | 大小:5kb | 下载:0
[VHDL编程] lab_instructions1
说明:The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The o<Gopi> 在 2025-03-16 上传 | 大小:1.13mb | 下载:0
[VHDL编程] lab_instructions2
说明:The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The o<Gopi> 在 2025-03-16 上传 | 大小:2.14mb | 下载:0
[VHDL编程] lab_instructions3
说明:The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The o<Gopi> 在 2025-03-16 上传 | 大小:1mb | 下载:0
[VHDL编程] Spartan-3ADSPs
说明:The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The o<Gopi> 在 2025-03-16 上传 | 大小:1016kb | 下载:0