搜索资源列表
PLL
- 基于FPGa实现一个数字锁相环，实现时钟恢复，具有较好的通用性。-pll
PLL
- 一个基于FPGA的设计，使用锁相环，可以输出多个不同频率的时钟-failed to translate
Matlabpll
- 基于Matlab的数字锁相环的仿真设计，一篇毕业论文，对数字和模拟锁相环进行了详细的分析和仿真-Matlab-based simulation of digital PLL design, a thesis on digital and analog phase-locked loop for a detailed analysis and simulation
PLLC
- 本程序利用平方环实现载波同步，使用锁相环进行跟踪相位偏移-This program makes use of the square ring to achieve carrier synchronization, with the use of PLL to track the phase shift
DesignoftrackingloopofGPSsoftwarereceiver
- 本文在分析GPS 软件接收机跟踪原理的基础上，首先比较码环与载波环不同鉴相器的性能，然后对二阶锁相环中不同环路参数设下的跟踪效果进行仿真分析，最后设计 了合适的码环与载波环路，并用实际采集的GPS 数据论证了所设计环路的有效性，为GPS 软件接收机跟踪环路的设计提供了参考。-Based on the analysis of GPS receiver tracking software on the basis of the prin
FPGA-based-design-of-DPLL
- 采用VHDL设计的全数字锁相环电路设计，步骤以及一些详细过程介绍。-VHDL design using all-digital PLL circuit design, detailed process steps and some introduction.
dpll
- 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
cp
- 清华大学锁相环课程课件，电荷泵电路设计部分。-Tsinghua University Courseware PLL, charge pump circuit part.
pllverilog
- 基于FPGA的程序编写，完成pll锁相环的设计，实验证明次程序是完整的-FPGA-based programming, complete pll PLL design, experiments show that second program is complete
Tracking
- 实现gps卫星的跟踪功能。载波跟踪环采用锁频环辅助下的锁相环，码跟踪环采用延迟锁相环。-Gps satellite tracking to achieve. Carrier tracking loop using the aid of frequency-locked loop PLL, code tracking loop using delay locked loop.
pll
- 数字通信中的锁相环（PLL）完整程序，包括噪声处理，可用于GPS的的跟踪和捕获-the matlab code of PLL ,including how to deal with the noise ,which can be used to acquiring and tracking on GPS
ADF4110_4111_4112_4113
- 基于单片机的锁相环编程，锁相环可用于倍频和锁相。(PLL programming based on single chip microcomputer, PLL can be used for frequency doubling and phase locking.)
PLL_simulink
- pll锁相环simulink模型，通俗易懂，可以实现的模型(Pll phase locked loop simulink model, easy to understand, can achieve the model)
锁相环PLL算法
- 该算法是介绍三相软件锁相环源代码，通过C编写(PLL algorithm source code)
one_phause_pll
- 描述： 单相锁相环仿真模型，适用于想了解PLL的同学。(a Phase Lock Loop (PLL) closed-loop control system, which tracks the frequency and phase of a sinusoidal signal by using an internal frequency oscillator. The control system adjusts the inter
pll
- 三相锁相环，应用于电力电子控制，锁相相位角用于3/2变换等(Three phase phase-locked loop is used in power electronic control, phase-locked phase angle is used for 3/2 transformation, etc.)
dpll源程序
- 一种设计数字锁相环的思路，包含异或鉴相器、k模可逆计数器、脉冲加减计数器、N分频器等，实现相位的锁定。(A design of digital phase locked loop (PLL) consists of a phase discriminator, a K mode reversible counter, a pulse addition and subtraction counter, a N frequency divi
PLLsuoxianghuan
- PLL锁相环的仿真，自己搭建的模型，可以有效实现相位的跟踪。(PLL simulation, build its own model, can effectively achieve phase tracking.)
TwoOderPll
- 1、资料包含二阶环路设计简要说明，Matlab程序，Matlab程序模拟FPGA工作方式，对各变量进行了量化处理 2、资料包含使用Vivado2015.4.2版本的工程文件，可直接运行查看仿真结果 3、参考资料为杜勇老师的《锁相环技术原理及其FPGA实现》(1. The data include a brief descr iption of the second-order loop design. The MATLAB prog
MINI_INV_v1
- 自己毕设用的单相并网逆变器程序，使用的是TI公司的DSP28335，包括了锁相环PLL，PR控制等子程序(The program of single-phase grid-connected inverters is designed by ourselves. It uses TI's DSP28335, including PLL, PR control and other subroutines.)