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数字锁相环设计源程序
- PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛,本例用VHDL描述了一个锁相环作为参考,源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上;顶层文件是PLL.GDF-digital phase-locked loop PLL design source, i
数字锁相环dll_code
- 通信系统中,信号捕获和同步的数字锁相环的MATLAB仿真程序-communications systems, signal acquisition and synchronization of digital PLL MATLAB simulation program
DPLL
- 数字锁相环DPLL实例程序,帮助理解PLL的结构和详细原理-DPLL DPLL examples of procedures to help understand the structure and PLL detailed Principle
PLLSim
- 二阶锁相环Matlab仿真代码,如入两路信号和信噪比,输出锁相以后的信号。可以仿真初始频差,和频率斜升的情况-second-order PLL Matlab simulation code, such as two-way signals and signal to noise ratio, the output signal after the lock-in. Simulation can initial frequency dif
PLLpro
- 关于数字锁相环的使用,结合FM,AM的使用来说明-DPLL on the use of combined FM and AM to illustrate the use of
dtf-test
- 89C54构成MC4511锁相环稳定性扫描测试仪器,-89C54 constitute MC4511 PLL stability scan testing equipment
DPLL1lp
- 频带数字通信中,频带一阶锁相环simulink模型-band digital communications, a frequency band PLL Simulink model
s72369
- 508a的控制锁相环的程序,这次不会重了吧 老子自己写的-508a of the PLL control procedures, this will never come to the point I wrote it myself
203.6M
- 508单片机,控制si4133单片锁相环产生203.6mhz的频率-508 microprocessor, control si4133 PLL frequency generated 203.6mhz
dig_pll
- 一个简易的数字锁相环,可以产生一个与输入同频同相的输出时钟-A simple digital PLL can generate an input in phase with the same frequency output clock
AD-PLL
- 基于VHDL的全数字锁相环的设计与实现,quartusII的仿真程序。-DPLL based on VHDL Design and Implementation, quartusII the simulation program.
a-new-digital-PLL
- 基于FPGA实现的一种新型数字锁相环设计。该设计是用VHDL来实现的,个人觉得不错,所以传上来和大家分享-FPGA-based implementation of a new digital PLL design. The design is to use VHDL to implement the individual feels good, so come and share transfer
PLL-Bible
- 本书是锁相环技术领域的经典著作,在前两版的基础上进行了大幅的改写和扩充。不仅对传统锁相技术重新进行了更深入的考察并增加了许多从未发表的新内容,反遇了近年来最新技术进展。本书的重点是讲解基本原理,同时详细介绍了频率捕获、电荷泵锁相环等热点应用问题。 本书主要适用于通信电子行业的工程技术人员以及高等院校相关专业师生。-Bible of phase locked loop technology
spll_simplest_IQ
- 利用科斯塔斯环实现软件锁相环,完成信号相位的跟踪-Costas loop using software PLL to achieve complete phase tracking signal
PLL
- 锁相环通信系统仿真 包括预处理,仿真引擎,以及后处理-PLL communication system simulation including pre-processing, simulation engines, and post-processing
PLL
- 一个基于二阶广义积分器的锁相环仿真模型,可以测得三相正弦信号的相位和频率(Phase-locked loop simulation model based on Nikai Hiroyoshi integrator)
锁相环频率合成
- 基于51单片机的锁相环频率合成器的设计。使用PLL集成芯片CD4046,可编程分频芯片CD4522(同MC14522),使用LCD1602显示,频率由按键输入。标准输入信号为1khz方波。(Design of PLL Frequency Synthesizer Based on 51 single chip microcomputer. Using PLL integrated chip CD4046, programmable fre
PLL
- 通过对输入时钟进行锁相环IP核配置,产生所需的时钟信号(By configuring the input clock PLL, the IP core generates the desired clock signal)
pll
- 自己用matlab编写的平方锁相环的仿真,对锁相环研究的同学具有很好的参考价值(The simulation of PLL written by myself in MATLAB is of great reference value to the students who study PLL.)
PLL
- 测量三相交流电源的线电压,使用PLL跟踪其相位或者频率,对于锁相环的设计和学习,有一定的参考价值。(Measuring the line voltage of three-phase AC power supply and tracking its phase or frequency with PLL are of certain reference value for the design and learning of PLL.)