搜索资源列表
DPLL
- 介绍了一宽带的数字锁相环的实现方法,欢迎大家踊跃下载 -Introduction of a broadband digital phase-locked loop method, enthusiastically welcomed the U.S. Download
lock
- 锁相环程序,可以用。 主要是c语言风格的,在 matlab下也可以用-PLL procedures can be used. Mainly c-style language in matlab can also be used under
digitalPLL
- 数字锁相环实现源码,有很大的参考价值。 由 鉴相器 模K加减计数器 脉冲加减电路 同步建立侦察电路 模N分频器 构成.-DPLL realize source, has a great reference value. By the phase detector counter modulus K addition and subtraction circuit synchronous pulse addition and sub
LMX2326
- 基于单片机控制锁相环的程序设计,采用AT89S52编程控制LMX2326-Single-chip PLL-based control procedures designed to control AT89S52 programming LMX2326
sendDataPLL
- 锁相环TB31202的c驱动程序,本人刚完成的项目采用的。运行正常!容易移植-TB31202 the c phase-locked loop driver, I have just completed the project adopted. Operating normally! Easy to transplant
dpll_demo
- 一个实现简单的数字锁相环Verilog代码,本人借鉴网上现有的代码后经修改在Cyclone II上调通实现,里面有ModelSim仿真成功的波形图-A simple digital PLL Verilog code, I draw on-line after the existing code, as amended, pass upward in the Cyclone II realized, there are successfu
A1
- 基于ADF4106的锁相环程序,4106由单片机C8051F530提供控制字,输出频率3.6GHz,已经在单班上进行过调试。-ADF4106 PLL-based procedures, 4106 to provide control by the single-chip C8051F530 word, the output frequency of 3.6GHz, has been carried out in a single cla
mc145170
- 这是锁相环芯片MC145170程序,单片机是用at89s52的-This is the procedure MC145170 PLL chip, microcontroller AT89S52 is the
div
- 分频器是FPGA设计中使用频率非常高的基本单元之一。尽管目前在大部分设计中还广泛使用集成锁相环(如altera的PLL,Xilinx的DLL)来进行时钟的分频、倍频以及相移设计,但是,对于时钟要求不太严格的设计,通过自主设计进行时钟分频的实现方法仍然非常流行。首先这种方法可以节省锁相环资源,再者,这种方式只消耗不多的逻辑单元就可以达到对时钟操作的目的。 偶数倍分频:偶数倍分频应该是大家都比较熟悉的分频,通过计数器计数是完全可以实
DPLL_verilog
- 一阶全数字锁相环VERLOGIC程序代码,调试通过。-First-order DPLL VERLOGIC program code, debugging through.
DIGTAL_FIR
- 环路滤波器的设计,基于FPGA的锁相环应用。-Loop filter design, FPGA-based PLL applications.
Matlab_model
- 在MATLAB环境下,对全数字锁相环的仿真,分析锁相环的性能参数-In the MATLAB environment, to all-digital phase-locked loop simulation, analysis of the performance parameters of phase-locked loop
ACarrierTrackingAlgorithmBasedOnFPLL
- 介绍了一种基于锁频锁相环(FPLL)的载波跟踪算法。频率跟踪模块可以适应较大动态范围的频率变化,基于软件的数控振荡器(NCO)模块可以达到极高的频率跟踪精度。由于有锁频环的频率牵引,锁相环路滤波器可以设计得很窄,具有很好的抑噪性能,满足精确跟踪载波相位的要求。因此,该基于FPLL的载波跟踪算法可以适应信号存在较大的动态范围和噪声干扰的应用环境;同时,其鉴频鉴相算法表达式简单,易于用可编程数字器件实现。-Introduce an appr
FrequencySynthesisbyPhaseLock
- 书籍频综和锁相环的Matlab源代码,对频综和锁相环的设计很有帮助;-Books PLL Frequency Synthesizer and the Matlab source code for PLL Frequency Synthesizer Design and helpful
shuzisuoxiang
- 数字锁相环(DPLL)技术在数字通信、无线电电子学等众多领域得到了极为广泛的应用。与传统的模拟电路实现的PLL相比,DPLL具有精度高、不受温度和电压影响、环路带宽和中心频率编程可调、易于构建高阶锁相环等优点。-Digital phase-locked loop (DPLL) technology in digital communications, radio electronics, and many other fields ha
Pllrrrr
- 锁相环(非科斯塔斯环) 对波动频率进行锁定,并且对信号进行解调。画图7个显示过程及参数-The phase locked loop(PLL),adjusts the phase of a local oscillator.the phase of the incoming signal is locked and the signal is demodulated show the process and reference
simple_pll_3
- 简单的模拟锁相环仿真,基于simulink平台使本地震荡频率跟上接收到得频率-analog pll simulation,based on simulink
PLL_grt_rtw
- C语言实现了数字锁相环的程序,不过程序比较复杂,得参照MATLAB中 Discrete 3-phase pll模型-C language implementation of the DPLL procedure, but more complicated procedures, may refer to MATLAB, Discrete 3-phase pll model
altpllpll
- 用VHDL语言编写的锁相环源代码,可用于配置FPGA,在FPGA中实现PLL功能。-VHDL language with PLL source code, can be used to configure the FPGA, PLL function is implemented in the FPGA.
QPSK4_Weitongbu
- 关于定时同步的Matlab仿真代码,采用锁相环技术实现-Matlab code for Timing recovery using PLL