搜索资源列表
PLLmatlab1
- 锁相环程序，用MATLAB 编写，用来防真琐相环的工作过程。有学习价值-A PLL S PROGRAM CODING IN MATLAB,WHICH CAN SIMULATE THE PROCESS OF PLL.IT S VALUABE FOR LEARNING
PLLprogram
- 数字锁相环程序，适合于FM、AM开发 数字锁相环程序，适合于FM、AM开发-DPLL procedures for FM, AM Development DPLL procedures for FM, AM Development
pll_LMX1601
- 一个汇编写的锁相环程序，直接用来控制国半的LMX1601芯片，也可参考控制其它PLL IC-a compilation of written procedures PLL directly used to control half the country LMX1601 chips, Reference may also control other PLL IC
verilogpll1234
- 基于verilog的全数字锁相环的设计，基于verilog的全数字锁相环的设计。-verilog DPLL the design, verilog based on the DPLL design.
PLL_System_Sim_for_matlab
- 仿真锁相环系统，可以仿真锁定时间。不同的环路带宽对系统的非理想特性！-PLL simulation system that can lock simulation time. Different loop bandwidth of the system of non-ideal characteristics!
pll
- 关于锁相环的MATLAB的仿真程序，其中有详细的注释，希望它能能对你的能有所帮助-PLL on the MATLAB simulation program, including a detailed Notes hope it can be your right, can be helped
VHDL_PLL
- 介绍了锁相环PLL的实现原理，可以为VHDL实现PLL提供参考。-introduced PLL PLL The principle for VHDL PLL reference.
matlab
- pll锁相环仿真程序，经过测试，并附上仿真图，值得学习-pll phase locked loop simulation program, tested with the simulation map, it is worth learning
PLL
- 自己写的一个锁相环程序，希望对大家有所帮助-A phase-locked loop to write their own procedures, we hope to be helpful
dpll
- 数字锁相环，采用costas环的数字形式，实现跟踪载波相位，-Digital phase-locked loop, using the digital form costas loop to achieve carrier phase tracking,
pll
- 仿真了锁相环工作到一定时间后达到锁定状态的过程，程序采用的是一阶RC低通滤波器即二阶一型环-Simulation of the PLL to work until after a certain period of time to achieve lock-state process, the procedure is used first-order RC low-pass filter that is second-order on
c8051f120_PLL
- c8051120锁相环，定时器3的初始化和使用-c8051120 PLL, timer initialization and use of 3
PLL
- 锁相环控制，用的IC是AT89C2051，用P1口做控制，不知大家有没兴趣-PLL control IC is used AT89C2051, using P1 control I do, I do not know you have no interest
costas_loop
- 使用改进的COSTAS环实现锁相环（PLL），应用于高动态的数字化接收系统-COSTAS Central improved to achieve phase-locked loop (PLL), used in high dynamic digital reception system
PLL
- 可以实现自动锁相环功能的C源程序代码模块，-Can be achieved automatically PLL function C source code modules,
timer_trigger_adc_PLL_SUCCESS
- DSP2407定时器触发ADC，并且进行软件锁相环的实现。-DSP2407 timer to trigger ADC, and the realization of a software phase-locked loop.
pll
- 关于数字锁相环方面的代码,觉得还可以，或许对大家有用-the code of the pll
suoxianghuan
- 锁相环（PLL）simulink仿真，加深对PLL的理解-Phase-locked loop (PLL) simulink simulation, to deepen understanding of the PLL
PLL(lin)
- 锁相环的设计主要用于载波跟踪代码，在载波跟踪捕获当中可能会用到的源代码-PLL design is mainly used for carrier tracking code, the carrier capture which may be used to track the source code
255
- 全数字锁相环的Verilog源代码，经过仿真调试-All-digital PLL Verilog source code, through the simulation to debug