文件名称:yunsuan-verilog
介绍说明－－下载内容均来自于网络，请自行研究使用
运算器的实现，即实验指导书中的实验一，文件中包含有原代码及端口设置（可变），用vrilog HDL编程，Xilinx ISE 6仿真，并在实际电路中得到实现．-operations for the realization of the experimental guidance of a book. document contains the original code and port settings (variable), with vrilog HDL programming, Xilinx ISE 6 simulation, and the actual circuit realization.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : 95302937yunsuan-verilog.rar 列表 yunsuan\adder-mdq\.untf yunsuan\adder-mdq\adder.bgn yunsuan\adder-mdq\adder.bit yunsuan\adder-mdq\adder.bld yunsuan\adder-mdq\adder.cmd_log yunsuan\adder-mdq\adder.dhp yunsuan\adder-mdq\adder.drc yunsuan\adder-mdq\adder.ipf yunsuan\adder-mdq\adder.ise yunsuan\adder-mdq\adder.ise_ISE_Backup yunsuan\adder-mdq\adder.lso yunsuan\adder-mdq\adder.mrp yunsuan\adder-mdq\adder.nc1 yunsuan\adder-mdq\adder.ncd yunsuan\adder-mdq\adder.ngc yunsuan\adder-mdq\adder.ngd yunsuan\adder-mdq\adder.ngm yunsuan\adder-mdq\adder.ngr yunsuan\adder-mdq\adder.pad yunsuan\adder-mdq\adder.pad_txt yunsuan\adder-mdq\adder.par yunsuan\adder-mdq\adder.pcf yunsuan\adder-mdq\adder.placed_ncd_tracker yunsuan\adder-mdq\adder.prj yunsuan\adder-mdq\adder.routed_ncd_tracker yunsuan\adder-mdq\adder.stx yunsuan\adder-mdq\adder.syr yunsuan\adder-mdq\adder.twr yunsuan\adder-mdq\adder.twx yunsuan\adder-mdq\adder.ucf yunsuan\adder-mdq\adder.ucf.untf yunsuan\adder-mdq\adder.ut yunsuan\adder-mdq\adder.v yunsuan\adder-mdq\adder.xpi yunsuan\adder-mdq\adder_last_par.ncd yunsuan\adder-mdq\adder_map.ncd yunsuan\adder-mdq\adder_map.ngm yunsuan\adder-mdq\adder_pad.csv yunsuan\adder-mdq\adder_pad.txt yunsuan\adder-mdq\adder_summary.html yunsuan\adder-mdq\adder_vhdl.prj yunsuan\adder-mdq\bitgen.ut yunsuan\adder-mdq\xst\work\hdllib.ref yunsuan\adder-mdq\xst\work\vlg54\adder.bin yunsuan\adder-mdq\_impact.cmd yunsuan\adder-mdq\_ngo\netlist.lst yunsuan\adder-mdq\__projnav\adder.gfl yunsuan\adder-mdq\__projnav\adder.xst yunsuan\adder-mdq\__projnav\adder_flowplus.gfl yunsuan\adder-mdq\__projnav\adder_ncdTOut_tcl.rsp yunsuan\adder-mdq\__projnav\bitgen.rsp yunsuan\adder-mdq\__projnav\ednTOngd_tcl.rsp yunsuan\adder-mdq\__projnav\nc1TOncd_tcl.rsp yunsuan\adder-mdq\__projnav\parentEditConstraintsTextApp_tcl.rsp yunsuan\adder-mdq\__projnav\runXst_tcl.rsp yunsuan\adder-mdq\__projnav\sumrpt_tcl.rsp yunsuan\Spartan-II Data Sheets.pdf yunsuan\Xilinx ISE7[1].1入门导读.pdf yunsuan\基于EDA-IV实验箱的FPGA开发流程.pdf yunsuan\实验指导书.doc yunsuan\实验教学大纲及汇总格式.doc yunsuan\数字系统.txt yunsuan\adder-mdq\xst\dump.xst\adder.prj\ngx\notopt yunsuan\adder-mdq\xst\dump.xst\adder.prj\ngx\opt yunsuan\adder-mdq\xst\dump.xst\adder.prj\ngx yunsuan\adder-mdq\xst\dump.xst\adder.prj yunsuan\adder-mdq\xst\work\vlg54 yunsuan\adder-mdq\xst\dump.xst yunsuan\adder-mdq\xst\work yunsuan\adder-mdq\xst yunsuan\adder-mdq\_ngo yunsuan\adder-mdq\_xmsgs yunsuan\adder-mdq\__projnav yunsuan\adder-mdq yunsuan