文件名称:yunsuan-verilog
- 所属分类：
- 其他嵌入式/单片机内容
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- [PDF]
- 上传时间：
- 2012-11-26
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- 1.53mb
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- 0次
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- 王*
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运算器的实现，即实验指导书中的实验一，文件中包含有原代码及端口设置（可变），用vrilog HDL编程，Xilinx ISE 6仿真，并在实际电路中得到实现．-operations for the realization of the experimental guidance of a book. document contains the original code and port settings (variable), with vrilog HDL programming, Xilinx ISE 6 simulation, and the actual circuit realization.
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yunsuan
.......\adder-mdq
.......\.........\.untf
.......\.........\adder.bgn
.......\.........\adder.bit
.......\.........\adder.bld
.......\.........\adder.cmd_log
.......\.........\adder.dhp
.......\.........\adder.drc
.......\.........\adder.ipf
.......\.........\adder.ise
.......\.........\adder.ise_ISE_Backup
.......\.........\adder.lso
.......\.........\adder.mrp
.......\.........\adder.nc1
.......\.........\adder.ncd
.......\.........\adder.ngc
.......\.........\adder.ngd
.......\.........\adder.ngm
.......\.........\adder.ngr
.......\.........\adder.pad
.......\.........\adder.pad_txt
.......\.........\adder.par
.......\.........\adder.pcf
.......\.........\adder.placed_ncd_tracker
.......\.........\adder.prj
.......\.........\adder.routed_ncd_tracker
.......\.........\adder.stx
.......\.........\adder.syr
.......\.........\adder.twr
.......\.........\adder.twx
.......\.........\adder.ucf
.......\.........\adder.ucf.untf
.......\.........\adder.ut
.......\.........\adder.v
.......\.........\adder.xpi
.......\.........\adder_last_par.ncd
.......\.........\adder_map.ncd
.......\.........\adder_map.ngm
.......\.........\adder_pad.csv
.......\.........\adder_pad.txt
.......\.........\adder_summary.html
.......\.........\adder_vhdl.prj
.......\.........\bitgen.ut
.......\.........\xst
.......\.........\...\dump.xst
.......\.........\...\........\adder.prj
.......\.........\...\........\.........\ngx
.......\.........\...\........\.........\...\notopt
.......\.........\...\........\.........\...\opt
.......\.........\...\work
.......\.........\...\....\hdllib.ref
.......\.........\...\....\vlg54
.......\.........\...\....\.....\adder.bin
.......\.........\_impact.cmd
.......\.........\_ngo
.......\.........\....\netlist.lst
.......\.........\_xmsgs
.......\.........\__projnav
.......\.........\.........\adder.gfl
.......\.........\.........\adder.xst
.......\.........\.........\adder_flowplus.gfl
.......\.........\.........\adder_ncdTOut_tcl.rsp
.......\.........\.........\bitgen.rsp
.......\.........\.........\ednTOngd_tcl.rsp
.......\.........\.........\nc1TOncd_tcl.rsp
.......\.........\.........\parentEditConstraintsTextApp_tcl.rsp
.......\.........\.........\runXst_tcl.rsp
.......\.........\.........\sumrpt_tcl.rsp
.......\Spartan-II Data Sheets.pdf
.......\Xilinx ISE7[1].1入门导读.pdf
.......\基于EDA-IV实验箱的FPGA开发流程.pdf
.......\实验指导书.doc
.......\实验教学大纲及汇总格式.doc
.......\数字系统.txt
.......\adder-mdq
.......\.........\.untf
.......\.........\adder.bgn
.......\.........\adder.bit
.......\.........\adder.bld
.......\.........\adder.cmd_log
.......\.........\adder.dhp
.......\.........\adder.drc
.......\.........\adder.ipf
.......\.........\adder.ise
.......\.........\adder.ise_ISE_Backup
.......\.........\adder.lso
.......\.........\adder.mrp
.......\.........\adder.nc1
.......\.........\adder.ncd
.......\.........\adder.ngc
.......\.........\adder.ngd
.......\.........\adder.ngm
.......\.........\adder.ngr
.......\.........\adder.pad
.......\.........\adder.pad_txt
.......\.........\adder.par
.......\.........\adder.pcf
.......\.........\adder.placed_ncd_tracker
.......\.........\adder.prj
.......\.........\adder.routed_ncd_tracker
.......\.........\adder.stx
.......\.........\adder.syr
.......\.........\adder.twr
.......\.........\adder.twx
.......\.........\adder.ucf
.......\.........\adder.ucf.untf
.......\.........\adder.ut
.......\.........\adder.v
.......\.........\adder.xpi
.......\.........\adder_last_par.ncd
.......\.........\adder_map.ncd
.......\.........\adder_map.ngm
.......\.........\adder_pad.csv
.......\.........\adder_pad.txt
.......\.........\adder_summary.html
.......\.........\adder_vhdl.prj
.......\.........\bitgen.ut
.......\.........\xst
.......\.........\...\dump.xst
.......\.........\...\........\adder.prj
.......\.........\...\........\.........\ngx
.......\.........\...\........\.........\...\notopt
.......\.........\...\........\.........\...\opt
.......\.........\...\work
.......\.........\...\....\hdllib.ref
.......\.........\...\....\vlg54
.......\.........\...\....\.....\adder.bin
.......\.........\_impact.cmd
.......\.........\_ngo
.......\.........\....\netlist.lst
.......\.........\_xmsgs
.......\.........\__projnav
.......\.........\.........\adder.gfl
.......\.........\.........\adder.xst
.......\.........\.........\adder_flowplus.gfl
.......\.........\.........\adder_ncdTOut_tcl.rsp
.......\.........\.........\bitgen.rsp
.......\.........\.........\ednTOngd_tcl.rsp
.......\.........\.........\nc1TOncd_tcl.rsp
.......\.........\.........\parentEditConstraintsTextApp_tcl.rsp
.......\.........\.........\runXst_tcl.rsp
.......\.........\.........\sumrpt_tcl.rsp
.......\Spartan-II Data Sheets.pdf
.......\Xilinx ISE7[1].1入门导读.pdf
.......\基于EDA-IV实验箱的FPGA开发流程.pdf
.......\实验指导书.doc
.......\实验教学大纲及汇总格式.doc
.......\数字系统.txt