文件名称:Verilog_EXAMPLE
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DesignWave 2005 8
Verilog Example
-Design Wave Verilog Example
Verilog Example
-Design Wave Verilog Example
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下载文件列表
压缩包 : 89346500verilog_example.zip 列表 01/ 01/chattering.vhd 02/ 02/MKEY_IN.vhd 03/ 03/D_IN.vhd 04/ 04/DOUT.vhd 05/ 05/hex2led_decoder.vhd 05/led.vhd 06/ 06/DMtxDrv.vhd 06/MDPGen.vhd 06/ReadMe.sjis.txt 06/ReadMe.txt 06/regDMtxDrv.vhd 06/rif_DMtxDrv.vhd 06/test_regDMtxDrv.vhd 06/VRamIF.vhd 07/ 07/ADCTES.vhd 08/ 08/PWMTES.vhd 09/ 09/dac902c.vhd 10/ 10/DAC7615C.vhd 11/ 11/delay.v 11/dispcont.v 11/in_buffers.v 11/io_buffers.v 11/lfsr.v 11/LFSR_top.qar 11/lfsr_top.v 11/loopcnt.v 11/main_state.v 11/out_buffers.v 11/pll3.v 11/pll5.v 11/pll6.v 11/read_state.v 11/ssram.v 11/write_state.v 12/ 12/PCIC.V 13/ 13/i2cBasics_package.vhd 13/i2cMaster.vhd 13/i2cMAU/ 13/i2cMAU/i2cDrv.vhd 13/i2cMAU/i2cRcv.vhd 13/i2cSlave.vhd 13/i2cStDec.vhd 13/ReadMe.sjis.txt 13/ReadMe.txt 13/regI2cMaster.vhd 13/regI2cSlave.vhd 13/rif_i2cMaster.vhd 13/rif_i2cSlave.vhd 13/verif/ 13/verif/SimRecord.ref.txt 13/verif/t_regI2cSM.vhd 13/verif/t_regI2cSM.vhd~