文件名称:Verilog_example
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本文件包括多路选择器器建模，译码器实验程序，加法器实验程序，比较器实验程序，计数器建模，I2C接口标准建模源码，串行接口RS232标准建模源码标准，LCM建模源码，时钟６分频源码，串并转化源码。
，对于硬件设计初学者来说有一定的参考价值。-This document includes MUX device modeling, experimental procedure decoder, adder experimental procedures, experimental procedures comparators, counters modeling, I2C interface standard modeling source, standard RS232 serial interface modeling source standards, LCM modeling source, clock frequency source 6, and transforming source string. For hardware design beginners have a certain reference value.
，对于硬件设计初学者来说有一定的参考价值。-This document includes MUX device modeling, experimental procedure decoder, adder experimental procedures, experimental procedures comparators, counters modeling, I2C interface standard modeling source, standard RS232 serial interface modeling source standards, LCM modeling source, clock frequency source 6, and transforming source string. For hardware design beginners have a certain reference value.
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下载文件列表
Verilog源码例子
...............\6分频
...............\.....\G5f.v
...............\.....\tb_g5f.v
...............\adder
...............\.....\ise
...............\.....\...\adder
...............\.....\...\.....\.untf
...............\.....\...\.....\adder.bgn
...............\.....\...\.....\adder.bit
...............\.....\...\.....\adder.bld
...............\.....\...\.....\adder.cmd_log
...............\.....\...\.....\adder.dhp
...............\.....\...\.....\adder.drc
...............\.....\...\.....\adder.lfp
...............\.....\...\.....\adder.lso
...............\.....\...\.....\adder.mrp
...............\.....\...\.....\adder.nc1
...............\.....\...\.....\adder.ncd
...............\.....\...\.....\adder.ngc
...............\.....\...\.....\adder.ngd
...............\.....\...\.....\adder.ngm
...............\.....\...\.....\adder.ngr
...............\.....\...\.....\adder.npl
...............\.....\...\.....\adder.pad
...............\.....\...\.....\adder.pad_txt
...............\.....\...\.....\adder.par
...............\.....\...\.....\adder.pcf
...............\.....\...\.....\adder.placed_ncd_tracker
...............\.....\...\.....\adder.prj
...............\.....\...\.....\adder.routed_ncd_tracker
...............\.....\...\.....\adder.stx
...............\.....\...\.....\adder.syr
...............\.....\...\.....\adder.twr
...............\.....\...\.....\adder.twx
...............\.....\...\.....\adder.ucf
...............\.....\...\.....\adder.ucf.untf
...............\.....\...\.....\adder.ut
...............\.....\...\.....\adder.v
...............\.....\...\.....\adder.xpi
...............\.....\...\.....\adder_map.ncd
...............\.....\...\.....\adder_map.ngm
...............\.....\...\.....\adder_pad.csv
...............\.....\...\.....\adder_pad.txt
...............\.....\...\.....\adder_vhdl.prj
...............\.....\...\.....\automake.log
...............\.....\...\.....\bitgen.ut
...............\.....\...\.....\xst
...............\.....\...\.....\...\work
...............\.....\...\.....\...\....\hdllib.ref
...............\.....\...\.....\...\....\vlg54
...............\.....\...\.....\...\....\.....\adder.bin
...............\.....\...\.....\_ngo
...............\.....\...\.....\....\netlist.lst
...............\.....\...\.....\__projnav
...............\.....\...\.....\.........\adder.gfl
...............\.....\...\.....\.........\adder.xst
...............\.....\...\.....\.........\adder_flowplus.gfl
...............\.....\...\.....\.........\adder_ncdTOut_tcl.rsp
...............\.....\...\.....\.........\bitgen.rsp
...............\.....\...\.....\.........\ednTOngd_tcl.rsp
...............\.....\...\.....\.........\map.log
...............\.....\...\.....\.........\nc1TOncd_tcl.rsp
...............\.....\...\.....\.........\par.log
...............\.....\...\.....\.........\parentAssignPackagePinsApp_tcl.rsp
...............\.....\...\.....\.........\posttrc.log
...............\.....\...\.....\.........\runXst_tcl.rsp
...............\.....\...\.....\__projnav.log
...............\.....\modelsim
...............\.....\........\adder.cr.mti
...............\.....\........\adder.mpf
...............\.....\........\vsim.wlf
...............\.....\........\work
...............\.....\........\....\adder
...............\.....\........\....\.....\verilog.asm
...............\.....\........\....\.....\_primary.dat
...............\.....\........\....\.....\_primary.vhd
...............\.....\........\....\tb_adder
...............\.....\........\....\........\verilog.asm
...............\.....\........\....\........\_primary.dat
...............\.....\........\....\........\_primary.vhd
...............\.....\........\....\_info
...............\.....\rtl
...............\.....\...\adder.v
...............\.....\...\tb_adder.v
...............\comparator
...............\..........\ISE
...............\..........\...\comparator
...............\..........\...\..........\.untf
...............\..........\...\..........\automake.log
...............\..........\...\..........\bitgen.ut
...............\..........\...\..........\comparator.bgn
...............\.
...............\6分频
...............\.....\G5f.v
...............\.....\tb_g5f.v
...............\adder
...............\.....\ise
...............\.....\...\adder
...............\.....\...\.....\.untf
...............\.....\...\.....\adder.bgn
...............\.....\...\.....\adder.bit
...............\.....\...\.....\adder.bld
...............\.....\...\.....\adder.cmd_log
...............\.....\...\.....\adder.dhp
...............\.....\...\.....\adder.drc
...............\.....\...\.....\adder.lfp
...............\.....\...\.....\adder.lso
...............\.....\...\.....\adder.mrp
...............\.....\...\.....\adder.nc1
...............\.....\...\.....\adder.ncd
...............\.....\...\.....\adder.ngc
...............\.....\...\.....\adder.ngd
...............\.....\...\.....\adder.ngm
...............\.....\...\.....\adder.ngr
...............\.....\...\.....\adder.npl
...............\.....\...\.....\adder.pad
...............\.....\...\.....\adder.pad_txt
...............\.....\...\.....\adder.par
...............\.....\...\.....\adder.pcf
...............\.....\...\.....\adder.placed_ncd_tracker
...............\.....\...\.....\adder.prj
...............\.....\...\.....\adder.routed_ncd_tracker
...............\.....\...\.....\adder.stx
...............\.....\...\.....\adder.syr
...............\.....\...\.....\adder.twr
...............\.....\...\.....\adder.twx
...............\.....\...\.....\adder.ucf
...............\.....\...\.....\adder.ucf.untf
...............\.....\...\.....\adder.ut
...............\.....\...\.....\adder.v
...............\.....\...\.....\adder.xpi
...............\.....\...\.....\adder_map.ncd
...............\.....\...\.....\adder_map.ngm
...............\.....\...\.....\adder_pad.csv
...............\.....\...\.....\adder_pad.txt
...............\.....\...\.....\adder_vhdl.prj
...............\.....\...\.....\automake.log
...............\.....\...\.....\bitgen.ut
...............\.....\...\.....\xst
...............\.....\...\.....\...\work
...............\.....\...\.....\...\....\hdllib.ref
...............\.....\...\.....\...\....\vlg54
...............\.....\...\.....\...\....\.....\adder.bin
...............\.....\...\.....\_ngo
...............\.....\...\.....\....\netlist.lst
...............\.....\...\.....\__projnav
...............\.....\...\.....\.........\adder.gfl
...............\.....\...\.....\.........\adder.xst
...............\.....\...\.....\.........\adder_flowplus.gfl
...............\.....\...\.....\.........\adder_ncdTOut_tcl.rsp
...............\.....\...\.....\.........\bitgen.rsp
...............\.....\...\.....\.........\ednTOngd_tcl.rsp
...............\.....\...\.....\.........\map.log
...............\.....\...\.....\.........\nc1TOncd_tcl.rsp
...............\.....\...\.....\.........\par.log
...............\.....\...\.....\.........\parentAssignPackagePinsApp_tcl.rsp
...............\.....\...\.....\.........\posttrc.log
...............\.....\...\.....\.........\runXst_tcl.rsp
...............\.....\...\.....\__projnav.log
...............\.....\modelsim
...............\.....\........\adder.cr.mti
...............\.....\........\adder.mpf
...............\.....\........\vsim.wlf
...............\.....\........\work
...............\.....\........\....\adder
...............\.....\........\....\.....\verilog.asm
...............\.....\........\....\.....\_primary.dat
...............\.....\........\....\.....\_primary.vhd
...............\.....\........\....\tb_adder
...............\.....\........\....\........\verilog.asm
...............\.....\........\....\........\_primary.dat
...............\.....\........\....\........\_primary.vhd
...............\.....\........\....\_info
...............\.....\rtl
...............\.....\...\adder.v
...............\.....\...\tb_adder.v
...............\comparator
...............\..........\ISE
...............\..........\...\comparator
...............\..........\...\..........\.untf
...............\..........\...\..........\automake.log
...............\..........\...\..........\bitgen.ut
...............\..........\...\..........\comparator.bgn
...............\.