文件名称:RISC_CPU
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VHDL语言设计的RISC_CPU，分为八个基本部件分模块构建，分别为时钟发生器，指令寄存器，累加器，算术逻辑运算单元，数据控制器，状态控制器，程序计数器以及地址多路器-The VHDL language RISC_CPU, is divided into eight basic components of modular construction, respectively, the clock generator, the instruction register, accumulator, arithmetic and logic unit, the data controller, the state controller, the program counter and address multiplexer
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下载文件列表
RISC_CPU\accumulator.vhd
........\addr.vhd
........\addr_decode.vhd
........\alu.vhd
........\clkchange.vhd
........\clk_gen.vhd
........\counter.vhd
........\cpumain.vhd
........\datactl.vhd
........\instruction_register.vhd
........\machine.vhd
........\machinectl.vhd
........\ram.vhd
........\rom.vhd
RISC_CPU
........\addr.vhd
........\addr_decode.vhd
........\alu.vhd
........\clkchange.vhd
........\clk_gen.vhd
........\counter.vhd
........\cpumain.vhd
........\datactl.vhd
........\instruction_register.vhd
........\machine.vhd
........\machinectl.vhd
........\ram.vhd
........\rom.vhd
RISC_CPU