文件名称:RISC_CPU
介绍说明－－下载内容均来自于网络，请自行研究使用
Verilog写的简单处理器QuartusII下可编译
//指令 操作码 源寄存器 目的寄存器 操作
// NOP 0000 xxxxx xxxxxx 空操作
//ADD 0001 src dest dest<=src+dest
//SUB 0010 src dest dest<=dest-src
//AND 0011 src dest dest<=src&&dest
//NOT 0100 src dest dest<=~src
//RD 0101 xxxxx dest dest<= memory[Add_R]
//WR 0110 src xxxxx memory[Add_R]<=src
//BR 0111 xxxxx xxxxx PC<=memory[Add_R]
//BRZ 1000 xxxxx xxxxx PC<=memory[Add_R]
//HALT 1111 xxxxx xxxxx 挂起至RST-Verilog写的简单处理器QuartusII下可编译
//指令 操作码 源寄存器 目的寄存器 操作
// NOP 0000 xxxxx xxxxxx 空操作
//ADD 0001 src dest dest<=src+dest
//SUB 0010 src dest dest<=dest-src
//AND 0011 src dest dest<=src&&dest
//NOT 0100 src dest dest<=~src
//RD 0101 xxxxx dest dest<= memory[Add_R]
//WR 0110 src xxxxx memory[Add_R]<=src
//BR 0111 xxxxx xxxxx PC<=memory[Add_R]
//BRZ 1000 xxxxx xxxxx PC<=memory[Add_R]
//HALT 1111 xxxxx xxxxx 挂起至RST
//指令 操作码 源寄存器 目的寄存器 操作
// NOP 0000 xxxxx xxxxxx 空操作
//ADD 0001 src dest dest<=src+dest
//SUB 0010 src dest dest<=dest-src
//AND 0011 src dest dest<=src&&dest
//NOT 0100 src dest dest<=~src
//RD 0101 xxxxx dest dest<= memory[Add_R]
//WR 0110 src xxxxx memory[Add_R]<=src
//BR 0111 xxxxx xxxxx PC<=memory[Add_R]
//BRZ 1000 xxxxx xxxxx PC<=memory[Add_R]
//HALT 1111 xxxxx xxxxx 挂起至RST-Verilog写的简单处理器QuartusII下可编译
//指令 操作码 源寄存器 目的寄存器 操作
// NOP 0000 xxxxx xxxxxx 空操作
//ADD 0001 src dest dest<=src+dest
//SUB 0010 src dest dest<=dest-src
//AND 0011 src dest dest<=src&&dest
//NOT 0100 src dest dest<=~src
//RD 0101 xxxxx dest dest<= memory[Add_R]
//WR 0110 src xxxxx memory[Add_R]<=src
//BR 0111 xxxxx xxxxx PC<=memory[Add_R]
//BRZ 1000 xxxxx xxxxx PC<=memory[Add_R]
//HALT 1111 xxxxx xxxxx 挂起至RST
(系统自动生成,下载前可以参看下载内容)
下载文件列表
RISC_CPU\RISC_CPU.asm.rpt
........\RISC_CPU.done
........\RISC_CPU.fit.rpt
........\RISC_CPU.fit.smsg
........\RISC_CPU.fit.summary
........\RISC_CPU.flow.rpt
........\RISC_CPU.map.rpt
........\RISC_CPU.map.smsg
........\RISC_CPU.map.summary
........\RISC_CPU.pin
........\RISC_CPU.pof
........\RISC_CPU.qpf
........\RISC_CPU.qsf
........\RISC_CPU.qws
........\RISC_CPU.sim.rpt
........\RISC_CPU.sof
........\RISC_CPU.tan.rpt
........\RISC_CPU.v
........\RISC_CPU.v.bak
........\RISC_CPU.vwf
........\test+RISC_CPU.v
........\test+RISC_CPU.v.bak
........\test_RISC_CPU.v
........\test_RISC_CPU.v.bak
........\Verilog1.v
........\Verilog1.v.bak
........\Waveform1.vwf
........\incremental_db\README
........\..............\compiled_partitions\RISC_CPU.root_partition.cmp.atm
........\..............\...................\RISC_CPU.root_partition.cmp.dfp
........\..............\...................\RISC_CPU.root_partition.cmp.hdbx
........\..............\...................\RISC_CPU.root_partition.cmp.kpt
........\..............\...................\RISC_CPU.root_partition.cmp.logdb
........\..............\...................\RISC_CPU.root_partition.cmp.rcf
........\..............\...................\RISC_CPU.root_partition.map.atm
........\..............\...................\RISC_CPU.root_partition.map.dpi
........\..............\...................\RISC_CPU.root_partition.map.hdbx
........\..............\...................\RISC_CPU.root_partition.map.kpt
........\db\prev_cmp_RISC_CPU.asm.qmsg
........\..\prev_cmp_RISC_CPU.fit.qmsg
........\..\prev_cmp_RISC_CPU.map.qmsg
........\..\prev_cmp_RISC_CPU.qmsg
........\..\prev_cmp_RISC_CPU.sim.qmsg
........\..\prev_cmp_RISC_CPU.tan.qmsg
........\..\RISC_CPU.ae.hdb
........\..\RISC_CPU.asm.qmsg
........\..\RISC_CPU.atom_map.rvd
........\..\RISC_CPU.cbx.xml
........\..\RISC_CPU.cmp.ecobp
........\..\RISC_CPU.cmp.kpt
........\..\RISC_CPU.cmp.rdb
........\..\RISC_CPU.cmp0.ddb
........\..\RISC_CPU.cmp_merge.kpt
........\..\RISC_CPU.db_info
........\..\RISC_CPU.eco.cdb
........\..\RISC_CPU.fit.qmsg
........\..\RISC_CPU.hier_info
........\..\RISC_CPU.hif
........\..\RISC_CPU.lpc.html
........\..\RISC_CPU.lpc.rdb
........\..\RISC_CPU.lpc.txt
........\..\RISC_CPU.map.ecobp
........\..\RISC_CPU.map.kpt
........\..\RISC_CPU.map.qmsg
........\..\RISC_CPU.map_bb.hdb
........\..\RISC_CPU.pre_map.cdb
........\..\RISC_CPU.pre_map.hdb
........\..\RISC_CPU.rpp.qmsg
........\..\RISC_CPU.rtlv.hdb
........\..\RISC_CPU.rtlv_sg.cdb
........\..\RISC_CPU.rtlv_sg_swap.cdb
........\..\RISC_CPU.sgate.rvd
........\..\RISC_CPU.sgate_sm.rvd
........\..\RISC_CPU.sgdiff.cdb
........\..\RISC_CPU.sgdiff.hdb
........\..\RISC_CPU.sim.cvwf
........\..\RISC_CPU.sim.hdb
........\..\RISC_CPU.sim.qmsg
........\..\RISC_CPU.sim.rdb
........\..\RISC_CPU.sld_design_entry.sci
........\..\RISC_CPU.sld_design_entry_dsc.sci
........\..\RISC_CPU.smp_dump.txt
........\..\RISC_CPU.syn_hier_info
........\..\RISC_CPU.tan.qmsg
........\..\RISC_CPU.tis_db_list.ddb
........\..\RISC_CPU_global_asgn_op.abo
........\..\wed.wsf
........\incremental_db\compiled_partitions
........\incremental_db
........\db
RISC_CPU
........\RISC_CPU.done
........\RISC_CPU.fit.rpt
........\RISC_CPU.fit.smsg
........\RISC_CPU.fit.summary
........\RISC_CPU.flow.rpt
........\RISC_CPU.map.rpt
........\RISC_CPU.map.smsg
........\RISC_CPU.map.summary
........\RISC_CPU.pin
........\RISC_CPU.pof
........\RISC_CPU.qpf
........\RISC_CPU.qsf
........\RISC_CPU.qws
........\RISC_CPU.sim.rpt
........\RISC_CPU.sof
........\RISC_CPU.tan.rpt
........\RISC_CPU.v
........\RISC_CPU.v.bak
........\RISC_CPU.vwf
........\test+RISC_CPU.v
........\test+RISC_CPU.v.bak
........\test_RISC_CPU.v
........\test_RISC_CPU.v.bak
........\Verilog1.v
........\Verilog1.v.bak
........\Waveform1.vwf
........\incremental_db\README
........\..............\compiled_partitions\RISC_CPU.root_partition.cmp.atm
........\..............\...................\RISC_CPU.root_partition.cmp.dfp
........\..............\...................\RISC_CPU.root_partition.cmp.hdbx
........\..............\...................\RISC_CPU.root_partition.cmp.kpt
........\..............\...................\RISC_CPU.root_partition.cmp.logdb
........\..............\...................\RISC_CPU.root_partition.cmp.rcf
........\..............\...................\RISC_CPU.root_partition.map.atm
........\..............\...................\RISC_CPU.root_partition.map.dpi
........\..............\...................\RISC_CPU.root_partition.map.hdbx
........\..............\...................\RISC_CPU.root_partition.map.kpt
........\db\prev_cmp_RISC_CPU.asm.qmsg
........\..\prev_cmp_RISC_CPU.fit.qmsg
........\..\prev_cmp_RISC_CPU.map.qmsg
........\..\prev_cmp_RISC_CPU.qmsg
........\..\prev_cmp_RISC_CPU.sim.qmsg
........\..\prev_cmp_RISC_CPU.tan.qmsg
........\..\RISC_CPU.ae.hdb
........\..\RISC_CPU.asm.qmsg
........\..\RISC_CPU.atom_map.rvd
........\..\RISC_CPU.cbx.xml
........\..\RISC_CPU.cmp.ecobp
........\..\RISC_CPU.cmp.kpt
........\..\RISC_CPU.cmp.rdb
........\..\RISC_CPU.cmp0.ddb
........\..\RISC_CPU.cmp_merge.kpt
........\..\RISC_CPU.db_info
........\..\RISC_CPU.eco.cdb
........\..\RISC_CPU.fit.qmsg
........\..\RISC_CPU.hier_info
........\..\RISC_CPU.hif
........\..\RISC_CPU.lpc.html
........\..\RISC_CPU.lpc.rdb
........\..\RISC_CPU.lpc.txt
........\..\RISC_CPU.map.ecobp
........\..\RISC_CPU.map.kpt
........\..\RISC_CPU.map.qmsg
........\..\RISC_CPU.map_bb.hdb
........\..\RISC_CPU.pre_map.cdb
........\..\RISC_CPU.pre_map.hdb
........\..\RISC_CPU.rpp.qmsg
........\..\RISC_CPU.rtlv.hdb
........\..\RISC_CPU.rtlv_sg.cdb
........\..\RISC_CPU.rtlv_sg_swap.cdb
........\..\RISC_CPU.sgate.rvd
........\..\RISC_CPU.sgate_sm.rvd
........\..\RISC_CPU.sgdiff.cdb
........\..\RISC_CPU.sgdiff.hdb
........\..\RISC_CPU.sim.cvwf
........\..\RISC_CPU.sim.hdb
........\..\RISC_CPU.sim.qmsg
........\..\RISC_CPU.sim.rdb
........\..\RISC_CPU.sld_design_entry.sci
........\..\RISC_CPU.sld_design_entry_dsc.sci
........\..\RISC_CPU.smp_dump.txt
........\..\RISC_CPU.syn_hier_info
........\..\RISC_CPU.tan.qmsg
........\..\RISC_CPU.tis_db_list.ddb
........\..\RISC_CPU_global_asgn_op.abo
........\..\wed.wsf
........\incremental_db\compiled_partitions
........\incremental_db
........\db
RISC_CPU