文件名称:risc_cpu
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这是一个Verilog HDL编写的RISC cpu的程序，该程序共10个子程序，实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。-This is the RISC cpu code which writed by Verilog HDL.This code has ten subprogram which
came true the simple RISC cpu. Beginner can reference this example to study the Hardware discr iption language and the design manner. This program have passed the Modelsim validate.
came true the simple RISC cpu. Beginner can reference this example to study the Hardware discr iption language and the design manner. This program have passed the Modelsim validate.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
test
....\cpu_admux.v
....\cpu_alu.v
....\cpu_clkg.v
....\cpu_datactrl.v
....\cpu_mem.v
....\cpu_pcounter.v
....\cpu_register.v
....\cpu_sctrl.v
....\cpu_top.v
....\test.cr.mti
....\test.mpf
....\transcript
....\vsim.wlf
....\work
....\....\@f@i@r@filter_1
....\....\...............\verilog.asm
....\....\...............\_primary.dat
....\....\...............\_primary.vhd
....\....\cpu_admux
....\....\.........\verilog.asm
....\....\.........\_primary.dat
....\....\.........\_primary.vhd
....\....\cpu_alu
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\cpu_clkg
....\....\........\verilog.asm
....\....\........\_primary.dat
....\....\........\_primary.vhd
....\....\cpu_datactrl
....\....\............\verilog.asm
....\....\............\_primary.dat
....\....\............\_primary.vhd
....\....\cpu_mem
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\cpu_pcounter
....\....\............\verilog.asm
....\....\............\_primary.dat
....\....\............\_primary.vhd
....\....\cpu_register
....\....\............\verilog.asm
....\....\............\_primary.dat
....\....\............\_primary.vhd
....\....\cpu_sctrl
....\....\.........\verilog.asm
....\....\.........\_primary.dat
....\....\.........\_primary.vhd
....\....\cpu_top
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\my@test
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\_info
....\cpu_admux.v
....\cpu_alu.v
....\cpu_clkg.v
....\cpu_datactrl.v
....\cpu_mem.v
....\cpu_pcounter.v
....\cpu_register.v
....\cpu_sctrl.v
....\cpu_top.v
....\test.cr.mti
....\test.mpf
....\transcript
....\vsim.wlf
....\work
....\....\@f@i@r@filter_1
....\....\...............\verilog.asm
....\....\...............\_primary.dat
....\....\...............\_primary.vhd
....\....\cpu_admux
....\....\.........\verilog.asm
....\....\.........\_primary.dat
....\....\.........\_primary.vhd
....\....\cpu_alu
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\cpu_clkg
....\....\........\verilog.asm
....\....\........\_primary.dat
....\....\........\_primary.vhd
....\....\cpu_datactrl
....\....\............\verilog.asm
....\....\............\_primary.dat
....\....\............\_primary.vhd
....\....\cpu_mem
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\cpu_pcounter
....\....\............\verilog.asm
....\....\............\_primary.dat
....\....\............\_primary.vhd
....\....\cpu_register
....\....\............\verilog.asm
....\....\............\_primary.dat
....\....\............\_primary.vhd
....\....\cpu_sctrl
....\....\.........\verilog.asm
....\....\.........\_primary.dat
....\....\.........\_primary.vhd
....\....\cpu_top
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\my@test
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\_info